Read latency and suspend modes

1. A memory system, comprising:

one or more memory devices; and

processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:

operate the memory system according to a first mode of operation associated with a first set of access operations comprising executing read operations, executing write operations, and suspending write operations;

receive, from a host system based at least in part on operating the memory system according to the first mode of operation, an indication to switch to a second mode of operation associated with a decreased latency for executing write operations based at least in part on limiting the suspending write operations;

identify that a register at the memory system is storing a threshold associated with limiting the suspending write operations based at least in part on receiving the indication to switch to the second mode of operation, the threshold being compared with a quantity of read operations performed during a write suspension duration; and

operate the memory system according to the second mode of operation based at least in part on receiving the indication and the threshold.

2. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:

select, from multiple modes of operation that are each associated with the decreased latency for executing write operations based at least in part on limiting the suspending write operations, the second mode of operation based at least in part on receiving the indication to switch to the second mode of operation, wherein operating the memory system according to the second mode of operation is based at least in part on the selecting.

3. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:

disable a suspension of write operations based at least in part on limiting the suspending write operations, wherein operating the memory system according to the second mode of operation is based at least in part on the disabling and comprises performing read operations and executing write operations.

4. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:

identify a threshold quantity of write operation suspensions for limiting the suspending write operations based at least in part on receiving the indication to switch to the second mode of operation, wherein the second mode of operation is associated with a second set of access operations comprising executing read operations, executing write operations, and suspending a quantity of write operations that is less than the threshold quantity of write operation suspensions.

5. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:

decrease a quantity of triggers associated with suspending write operations to limit the suspending write operations based at least in part on receiving the indication to switch to the second mode of operation, wherein the second mode of operation is associated with a second set of access operations comprising executing read operations, executing write operations, and suspending write operations in response to the decreased quantity of triggers.

6. The memory system of claim 1 , wherein receiving the indication to switch to the second mode of operation further comprises the processing circuitry configured to cause the memory system to:

receive a command comprising the indication to switch to the second mode of operation.

7. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:

transmit, to the host system, a second indication of a write execution latency based at least in part on operating the memory system according to the first mode of operation, wherein receiving the indication to switch to the second mode of operation is based at least in part on transmitting the second indication of the write execution latency.

8. The memory system of claim 1 , wherein:

the first set of access operations comprises suspending erase operations; and

the second mode of operation is associated with a decreased latency for executing erase operations based at least in part on limiting the suspending erase operations.

9. A host system, comprising:

processing circuitry configured to couple with a memory system, wherein the processing circuitry is configured to cause the host system to:

identify a first write execution latency associated with the memory system that is operating according to a first mode of operation associated with a first set of access operations comprising executing read operations, executing write operations, and suspending write operations;

transmit, to the memory system based at least in part on the identifying, an indication to switch to a second mode of operation associated with a decreased latency for executing write operations based at least in part on limiting the suspending write operations, wherein the transmitting comprises writing, to a register at the memory system, a threshold associated with limiting the suspending write operations, the threshold compared with a quantity of read operations performed during a write suspension duration; and

determine, based at least in part on transmitting the indication, whether a second write execution latency associated with the memory system that is operating according to the second mode of operation is less than the first write execution latency.

10. The host system of claim 9 , wherein transmitting the indication to switch to the second mode of operation further comprises the processing circuitry configured to cause the host system to:

transmit a command comprising the indication to switch to the second mode of operation.

11. The host system of claim 9 , wherein the processing circuitry is further configured to cause the host system to:

receive, from the memory system, a second indication of the first write execution latency, wherein identifying the first write execution latency is based at least in part on receiving the second indication.

12. The host system of claim 9 , wherein the processing circuitry is further configured to cause the host system to:

determine whether the first write execution latency exceeds a second threshold, wherein transmitting the indication to switch to the second mode of operation is based at least in part on determining that the first write execution latency exceeds the second threshold.

13. A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to:

operate the electronic device according to a first mode of operation associated with a first set of access operations comprising executing read operations, executing write operations, and suspending write operations;

receive, from a host system based at least in part on operating the electronic device according to the first mode of operation, an indication to switch to a second mode of operation associated with a decreased latency for executing write operations based at least in part on limiting the suspending write operations;

identify that a register at the electronic device is storing a threshold associated with limiting the suspending write operations based at least in part on receiving the indication to switch to the second mode of operation, the threshold being compared with a quantity of read operations performed during a write suspension; and

operate the electronic device according to the second mode of operation based at least in part on receiving the indication and the threshold.

14. The non-transitory computer-readable medium of claim 13 , wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to:

select, from multiple modes of operation that are each associated with the decreased latency for executing write operations based at least in part on limiting the suspending write operations, the second mode of operation based at least in part on receiving the indication to switch to the second mode of operation, wherein operating the electronic device according to the second mode of operation is based at least in part on the selecting.

15. The non-transitory computer-readable medium of claim 13 , wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to:

disable a suspension of write operations based at least in part on limiting the suspending write operations, wherein operating the electronic device according to the second mode of operation is based at least in part on the disabling and comprises performing read operations and executing write operations.

16. The non-transitory computer-readable medium of claim 13 , wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to:

identify a threshold quantity of write operation suspensions for limiting the suspending write operations based at least in part on receiving the indication to switch to the second mode of operation, wherein the second mode of operation is associated with a second set of access operations comprising executing read operations, executing write operations, and suspending a quantity of write operations that is less than the threshold quantity of write operation suspensions.

17. The non-transitory computer-readable medium of claim 13 , wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to:

decrease a quantity of triggers associated with suspending write operations to limit the suspending write operations based at least in part on receiving the indication to switch to the second mode of operation, wherein the second mode of operation is associated with a second set of access operations comprising executing read operations, executing write operations, and suspending write operations in response to the decreased quantity of triggers.

18. A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to:

identify a first write execution latency associated with a memory system that is operating according to a first mode of operation associated with a first set of access operations comprising executing read operations, executing write operations, and suspending write operations;

transmit, to the memory system based at least in part on the identifying, an indication to switch to a second mode of operation associated with a decreased latency for executing write operations based at least in part on limiting the suspending write operations, wherein the transmitting comprises writing, to a register at the memory system, a threshold associated with limiting the suspending write operations, the threshold compared with a quantity of read operations performed during a write suspension duration; and

determine, based at least in part on transmitting the indication, whether a second write execution latency associated with the memory system that is operating according to the second mode of operation is less than the first write execution latency.

19. The non-transitory computer-readable medium of claim 18 , wherein the instructions to transmit the indication to switch to the second mode of operation, when executed by the processing circuitry of the electronic device, further cause the electronic device to:

transmit a command comprising the indication to switch to the second mode of operation.

20. A memory system, comprising:

Rail one or more memory devices; and

processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:

operate the memory system according to a first mode of operation associated with a first set of access operations comprising executing read operations, executing write operations, and suspending write operations;

receive, from a host system based at least in part on operating the memory system according to the first mode of operation, an indication to switch to a second mode of operation associated with a decreased latency for executing write operations based at least in part on limiting the suspending write operations;

identify a threshold quantity of read operations performed during a write suspension duration, the threshold quantity of read operations to limit the suspending write operations based at least in part on receiving the indication to switch to the second mode of operation, wherein the second mode of operation is associated with a second set of access operations comprising executing read operations, executing write operations, and executing fewer read operations than the threshold quantity of read operations while suspending write operations; and

operate the memory system according to the second mode of operation based at least in part on receiving the indication.

21. A memory system, comprising:

one or more memory devices; and

processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:

operate the memory system according to a first mode of operation associated with a first set of access operations comprising executing read operations, executing write operations, and suspending write operations;

receive, from a host system based at least in part on operating the memory system according to the first mode of operation, an indication to switch to a second mode of operation associated with a decreased latency for executing write operations based at least in part on limiting the suspending write operations;

enable a cache associated with executing the write operations based at least in part on receiving the indication to switch to the second mode of operation; and

operate the memory system according to the second mode of operation based at least in part on receiving the indication and enabling the cache.

22. A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to:

operate the electronic device according to a first mode of operation associated with a first set of access operations comprising executing read operations, executing write operations, and suspending write operations;

receive, from a host system based at least in part on operating the electronic device according to the first mode of operation, an indication to switch to a second mode of operation associated with a decreased latency for executing write operations based at least in part on limiting the suspending write operations;

identify a threshold quantity of read operations performed during a write suspension duration, the threshold quantity of read operations to limit the suspending write operations based at least in part on receiving the indication to switch to the second mode of operation, wherein the second mode of operation is associated with a second set of access operations comprising executing read operations, executing write operations, and executing fewer read operations than the threshold quantity of read operations while suspending write operations; and

operate the electronic device according to the second mode of operation based at least in part on receiving the indication.