Semiconductor structure and method for forming features in redundant region of double seal ring
A semiconductor structure is provided. The semiconductor structure includes two circuit regions, two inner seal rings, an outer seal ring, a first redundant region, and an electrical circuit. Each of the inner seal rings surrounding one of the circuit regions. The outer seal ring is disposed around the inner seal rings, and each of the inner seal rings contacts the outer seal ring at different interior corners of the outer seal ring. The first redundant region is located between at least one of the inner seal rings and the outer seal ring. The electrical circuit is formed in the first redundant region and electrically connected to at least one of the circuit regions.
1. A semiconductor structure, comprising:
two circuit regions;
two inner seal rings, each of the inner seal rings surrounding one of the circuit regions;
an outer seal ring disposed around the inner seal rings, wherein each of the inner seal rings contacts the outer seal ring at different interior corners of the outer seal ring;
a first redundant region located between at least one of the inner seal rings and the outer seal ring; and
an electrical circuit formed in the first redundant region and electrically connected to at least one of the circuit regions.
2. The semiconductor structure of claim 1 , further comprising:
a second redundant region located between an edge of each of the inner seal rings, wherein the edges are opposite to and substantially parallel to each other.
3. The semiconductor structure of claim 2 , wherein the semiconductor structure is configured to be diced along a scribe line in the second redundant region and through the outer seal ring.
4. The semiconductor structure of claim 1 , wherein each of the inner seal rings has an opening, the openings are substantially aligned with each other, and the semiconductor structure further comprises:
interconnects that go through the openings and electrically connect the circuit regions.
5. The semiconductor structure of claim 4 , wherein the semiconductor structure is configured to be diced along an area that is outside of the outer seal ring.
6. The semiconductor structure of claim 1 , wherein the electrical circuit is formed in each layer of the semiconductor structure in which vertically protruding circuit features are present at the circuit regions.
7. The semiconductor structure of claim 1 , further comprising a pattern formed in the first redundant region, wherein the electrical circuit and the pattern are formed on different sides of the first redundant region.
8. The semiconductor structure of claim 1 , wherein the electrical circuit located at two vertically adjacent layers of the semiconductor structure is vertically connected.
9. A semiconductor structure, comprising:
two circuit regions;
two inner seal rings, each of the inner seal rings surrounding one of the circuit regions;
an outer seal ring disposed around the inner seal rings, wherein each of the inner seal rings contacts the outer seal ring at different interior corners of the outer seal ring;
a first redundant region located between at least one of the inner seal rings and the outer seal ring; and
a pattern formed in the first redundant region, wherein the distribution density of the pattern in the first redundant region is non-uniform across the first redundant region.
10. The semiconductor structure of claim 9 , wherein the pattern comprises an electrical circuit electrically connected to at least one of the circuit regions.
11. The semiconductor structure of claim 9 , wherein the pattern comprises homocentric squares, an L-shaped structure, or a cross structure.
12. The semiconductor structure of claim 9 , wherein the pattern comprises a plurality of strips arranged parallel to each other, and the lengths of the strips are different.
13. The semiconductor structure of claim 9 , wherein the pattern is present at least in one of a fin layer, a gate layer, a contact layer, via layers, and metal layers of the semiconductor structure.
14. The semiconductor structure of claim 9 , further comprising:
a second redundant region located between an edge of each of the inner seal rings, wherein the edges are opposite to and substantially parallel to each other.
15. The semiconductor structure of claim 14 , wherein the pattern is formed in the first redundant region and the second redundant region, wherein the distribution density of the pattern in the second redundant region is non-uniform across the second redundant region.
16. A semiconductor structure, comprising:
two circuit regions;
two inner seal rings, each of the inner seal rings surrounding one of the circuit regions;
an outer seal ring disposed around the inner seal rings, wherein the outer seal ring comprises four corner seal ring (CSR) structures in contact with either of the inner seal rings;
a first redundant region and a second redundant region separated by one of the CSR structures and one of the inner seal rings; and
two electrical circuits each formed in the first redundant region and the second redundant region and electrically connected to at least one of the circuit regions.
17. The semiconductor structure as claimed in claim 16 , wherein the inner seal rings are formed with a plurality of openings, and the openings are away from the first redundant region and the second redundant region.
18. The semiconductor structure as claimed in claim 17 , further comprising:
a plurality of interconnects connecting the circuit regions through the openings.
19. The semiconductor structure as claimed in claim 16 , wherein the outer seal ring comprises a plurality of sub seal rings, and the sub seal rings and the electrical circuits are disposed on the same level.
20. The semiconductor structure as claimed in claim 19 , wherein one of the sub seal rings is wider than another of the sub seal rings.