Storage device for executing processing code and operating method of the storage device
An operating method of a storage device, including a core and a memory, includes receiving a first processing code configured to enable execution of a first task and storing the first processing code in a first logical unit separately allocated in the memory for near-data processing (NDP), in response to a write command received from a host device, activating the core for executing the first processing code, in response to an activation command received from the host device, and executing the first task by using the core, in response to an execution command received from the host device.
1. An operating method of a storage device including a core and a memory that is a non-volatile memory, the operating method comprising:
receiving a first processing code configured to enable execution of a first task and storing the first processing code in a first logical unit separately allocated in the memory for near-data processing (NDP), in response to a write command received from a host device;
activating the core for executing the first processing code, in response to an activation command received from the host device; and
executing the first task by using the core, in response to an execution command received from the host device,
wherein the activating of the core is performed when the core is in an idle status,
wherein the storage device comprises a memory controller including the core, and
wherein the storing of the first processing code comprises:
checking, by using the memory controller, a size of the first processing code based on the write command; and
segmenting and receiving, by using the memory controller, the first processing code by a number of times corresponding to a size of the first processing code.
2. The operating method of claim 1 , wherein the storage device further comprises a sub-memory tightly coupled to the core, and
the checking of the size of the first processing code comprises:
comparing, by using the memory controller, a unit storage size of the sub-memory with the size of the first processing code; and
transferring, by using the memory controller, a ready-to-transfer response equal to the number of times, corresponding to the size of the first processing code, to the host device.
3. The operating method of claim 1 , further comprising:
receiving a second processing code configured to enable execution of a second task from the host device; and
storing the second processing code in a second logical unit separately allocated in the memory for the NDP.
4. The operating method of claim 1 , wherein:
the storage device further comprises a sub-memory tightly coupled to the core,
the activation command further comprises a fetch command, and further comprising:
fetching the first processing code loaded to the sub-memory based on the fetch command.
5. The operating method of claim 4 , wherein the fetching of the first processing code comprises:
storing the fetch command in a queue; and
performing, by using the core, fetch from the sub-memory on the basis of the fetch command in accordance with an order of the queue.
6. The operating method of claim 1 , wherein the idle status is a status where the core does not perform a memory operation including a read operation, a write operation, or an erase operation.
7. The operating method of claim 1 , wherein the executing of the first task comprises:
storing a task result in a second logical unit allocated for user data; and
transferring an address, at which the task result is stored, to the host device.
8. The operating method of claim 1 , wherein the first logical unit is included in a standard function area.
9. The operating method of claim 1 , wherein the first task comprises compression, encryption, quantization, a matrix operation, floating point conversion, tree search, swap, repetition removal, pruning, rendering, or data mining.
10. The operating method of claim 1 , wherein the first task is reprogrammable.
11. An operating method of a storage device having a non-volatile memory and a core, the operating method comprising:
receiving an encryption code, obtained by encrypting a processing code configured to execute a task, from a host device;
verifying a hash value of the encryption code based on a private key, and obtaining the processing code by decrypting the encryption code based on verification success;
storing the processing code in a first logical unit separately allocated in the memory for near-data processing (NDP);
fetching the processing code from the first logical unit;
when the core is in an idle status, activating the core; and
performing the task by using the core.
12. The operating method of claim 11 , wherein the receiving of the encryption code comprises:
determining an encryption method and providing a public key to the host device, on the basis of a public key request of the host device; and
receiving the encryption code, obtained through encryption based on the public key, from the host device.
13. The operating method of claim 11 , wherein a method of encrypting the encryption code comprises at least one of a Rivest-Shamir-Adleman (RSA) encryption method, a secure hash algorithm (SHA) encryption method, an error correction code (ECC) encryption method, and a digital signature algorithm (DSA) encryption method.
14. The operating method of claim 11 , wherein the storage device further comprises a sub-memory tightly coupled to the core, and
the activating of the core comprises:
loading the processing code, stored in the first logical unit, to the sub-memory; and
interpreting the processing code by using the core.
15. A storage device comprising a memory controller and a memory device, wherein:
the memory controller comprises:
a core;
a sub-memory tightly coupled to the core; and
a non-volatile main memory connected to the core and the sub-memory, wherein:
the memory device is a first logical unit, is separately allocated for near-data processing (NDP), and is configured to store a processing code for executing a task, and
the core is configured to execute the task based on the processing code stored in the first logical unit,
wherein the core is configured to be activated when the core is in an idle status, and
wherein the storing of the processing code comprises:
checking, by using the memory controller, a size of the processing code based on a write command; and
segmenting and receiving, by using the memory controller, the processing code by a number of times corresponding to a size of the processing code.
16. The storage device of claim 15 , wherein the task is executed when the core is in an idle status.
17. The storage device of claim 15 , wherein the memory device comprises:
a boot area;
a user data area; and
a standard function area, and
the first logical unit is included in the standard function area.
18. The storage device of claim 17 , wherein the core is configured to store an execution result of the task in a second logical unit included in the user data area.