HEMT transistor of the normally off type including a trench containing a gate region and forming at least one step, and corresponding manufacturing method
A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.
1. A normally off heterostructure field-effect transistor (HEMT), comprising:
a semiconductor heterostructure including:
a first semiconductor layer formed by gallium nitride; and
a second semiconductor layer formed by aluminum gallium nitride;
a passivation layer of dielectric material on the semiconductor heterostructure;
a trench in the passivation layer and the semiconductor heterostructure, the trench including:
a bottom surface;
a planar vertical sidewall in the semiconductor heterostructure on a first side of the trench; and
a plurality of first steps each including a respective horizontal surface higher in the trench than the bottom surface and a respective vertical surface laterally opposite the planar vertical sidewall on a second side of the trench in the semiconductor heterostructure, wherein the planar vertical sidewall extends entirely through the second semiconductor layer.
2. The HEMT of claim 1 , further comprising:
a dielectric layer on the planar vertical sidewall and the plurality of first steps; and
a conductive gate region on the dielectric layer in the trench.
3. The HEMT of claim 2 , wherein the dielectric layer is on a top surface of the passivation layer, wherein the conductive gate region is on the dielectric layer on the top surface of the passivation layer.
4. The HEMT of claim 1 , wherein the plurality of first steps are in the second semiconductor layer.
5. The HEMT of claim 1 , wherein the planar vertical sidewall extends partially into the first semiconductor layer.
6. The HEMT according to claim 1 , wherein the first and second semiconductor layers are of two materials that are configured to generate a two-dimensional electron gas in the first semiconductor layer.
7. The HEMT of claim 1 , further comprising a source metallization extending through the passivation layer and contacting the second semiconductor layer.
8. A normally off heterostructure field-effect transistor (HEMT), comprising:
a semiconductor heterostructure including:
a first semiconductor layer; and
a second semiconductor layer on the first semiconductor layer;
a passivation layer of dielectric material on the semiconductor heterostructure;
a trench extending entirely through the passivation layer, entirely through the second semiconductor layer, and partially through the first semiconductor layer, the trench including:
a bottom surface;
a planar first sidewall extending entirely through the second semiconductor layer; and
a plurality of steps, each step including a horizontal surface higher in the trench than the bottom surface and a vertical surface laterally opposite the first sidewall on a second side of the trench in the second semiconductor layer;
a dielectric layer coating the first sidewall and the plurality of steps;
a conductive gate on the dielectric layer and filling the trench; and
a source metalization extending through the passivation layer and in contact with the second semiconductor layer.
9. The HEMT of claim 8 , wherein the first and second semiconductor layers include, respectively, gallium nitride and aluminum gallium nitride.
10. A normally off heterostructure field-effect transistor (HEMT), comprising:
a semiconductor heterostructure including:
a first semiconductor layer; and
a second semiconductor layer on the first semiconductor layer;
a passivation layer of dielectric material on the semiconductor heterostructure;
a trench extending entirely through the passivation layer, entirely through the second semiconductor layer, and partially through the first semiconductor layer, the trench including:
a bottom surface;
a first step on a first side of the trench, the first step having a horizontal surface higher in the trench than the bottom surface;
a plurality of second steps on a second side of the trench each having a respective horizontal surface higher in the trench than the bottom surface;
a dielectric layer coating the first and second steps;
a conductive gate region on the dielectric layer and filling the trench; and
a source metallization extending through the passivation layer and in contact with the second semiconductor layer.
11. The HEMT of claim 10 , wherein the first and second semiconductor layers include, respectively, gallium nitride and aluminum gallium nitride.
12. The HEMT according to claim 10 , wherein the first and second semiconductor layers are of two materials that are configured to generate a two- dimensional electron gas in the first semiconductor layer.
13. The HEMT of claim 10 , wherein the dielectric layer is on a top surface of the passivation layer, wherein the conductive gate region is on the dielectric layer on the top surface of the passivation layer.
14. The HEMT of claim 10 , wherein the plurality of second steps are in the second semiconductor layer.
15. The HEMT of claim 10 , wherein the first step is in the first semiconductor layer.