Granted Patent B2

US 11,751,481 · App. 17/403,745 · Granted Sep 5, 2023

Inventor: Satoru Araki (San Jose, CA)

Assignee: Integrated Silicon Solution, (Cayman) Inc.

H10N50/01G11C11/161H01F10/329H01F10/3259H01F10/3286H01F41/32H10B61/22H10N50/10H10N50/80G11C11/1657G11C11/1673H10N50/85

Abstract

Claims (57)

1. A method of manufacturing a memory cell array comprising:

forming an array of selectors on a substrate;

forming a plurality of word lines on the substrate, the plurality of word lines being coupled to the array of selectors in respective rows;

forming a plurality of source lines on the substrate, the plurality of source lines being coupled to the array of selectors in respective columns;

forming a plurality of levels of Magnetic Tunnel Junction (MTJ) cells, including forming each level of MTJ cells by:

providing a planar insulator layer on the array of selectors and the plurality of word lines and the plurality of source lines;

forming a plurality of vias through the planar insulator layer;

forming a planar reference magnetic layer on the planar insulator layer;

forming a plurality of trenches in the planar reference magnetic layer;

forming a plurality of portions of a tunnel insulator layer and a free magnetic layer on the sidewalls of the plurality of trenches within the planar reference magnetic layer, adjacent portions of the tunnel insulator layer and the free magnetic layer being separated by an insulator block formed in the trenches; and

forming a plurality of a conductive core in the plurality of trenches adjacent corresponding portions of the free magnetic layer in the trenches within the planar reference magnetic layer; and

forming a plurality of bit lines, each bit line being in contact with the planar reference magnetic layer at each level.

2. The method of manufacturing a memory cell array according to claim 1 , wherein forming each level of MTJ cells comprises:

depositing the planar reference magnetic layer on the planar insulator layer;

forming the plurality of trenches through the reference magnetic layer;

forming the tunnel insulator layer on the sidewalls of the plurality of trenches and forming the free magnetic layer on the tunnel insulator layer;

selectively removing one or more portions of the tunnel insulator layer and one or more corresponding portions of the free magnetic layer;

forming a plurality of insulator blocks between separated portions of the tunnel insulator layer and corresponding portions of the free magnetic layer; and

forming the plurality of the conductive cores between the plurality of insulator blocks in the plurality of trenches.

3. The method of manufacturing a memory cell array according to claim 2 , wherein each of the trenches has a taper of approximately 10-45 degrees from a first side of the planar reference magnetic layer to a second side of the planar reference magnetic layer.

4. The method of manufacturing a memory cell array according to claim 2 , wherein forming each level of MTJ cells further comprises:

forming a non-magnetic layer on the free magnetic layer inside the trenches prior to selectively removing one or more portions of the tunnel insulator layer and the free magnetic layer,

wherein selectively removing one or more portions of the tunnel insulator layer and the free magnetic layer further comprises removing one or more corresponding portions of the non-magnetic layer;

forming the plurality of insulator blocks comprises forming the insulator blocks between the separated portions of the tunnel insulator layer, free magnetic layer, and non-magnetic layer; and

forming the plurality of conductive cores comprises forming the plurality of conductive cores on the portions of the non-magnetic layer separated by the one or more insulator blocks in the trench.

5. The method of manufacturing a memory cell array according to claim 4 , wherein the tunnel insulator layer comprises one or more layers of one or more of Magnesium Oxide (MgO), Silicon Oxide (SiOx), Aluminum Oxide (AlOx), and Titanium Oxide (TiOx), the free magnetic layer comprises one or more layers of one or more of Cobalt-Iron-Boron (Co—Fe—B), Cobalt-Nickle-Iron (CoNiFe), and Nickle-Iron (NiFe), and the non-magnetic layer comprises one or more layers of Ta, Cr, W, V, Pt, Ru, Pd, Cu, Ag, Rh, and their alloys.

6. The method of manufacturing a memory cell array according to claim 1 , wherein a formed MTJ cell in the manufactured memory cell array is further configured to be written to a logic “0” state by:

biasing a respective bit line at a bit line write potential;

biasing a respective source line at a ground potential; and

driving a respective word line at a word line write potential.

7. The method of manufacturing a memory cell array according to claim 6 , wherein a formed MTJ cell in the manufactured memory cell array is further configured to be written to a logic “0” state by:

biasing word lines for cells that are not being written to a ground potential; and

biasing other source lines at a high potential equaling to the bit line write potential.

8. The method of manufacturing a memory cell array according to claim 1 , wherein a formed MTJ cell in the manufactured memory cell array is further configured to be written to a logic “0” state by:

biasing a respective bit line of the MTJ cell at a bit line write potential;

biasing a respective source line of the MTJ cell at a ground potential; and

biasing a respective bit line of a following MTJ cell at a ground potential, resulting in half of a current that flows from the respective bit line of the MTJ cell, flowing out the respective source line of the MTJ, and half of the current leaking out through the respective bit line of the following MTJ cell, wherein the MTJ and the following MTJ cell are coupled in a string.

9. The method of manufacturing a memory cell array according to claim 1 , wherein a formed MTJ cell in the manufactured memory cell array is further configured to be written to a logic “0” state by:

biasing a respective bit line of the MTJ cell at a bit line write potential;

biasing a respective source line of the MTJ cell at a ground potential; and

biasing a respective bit line of a following MTJ cell at a potential that is half of the bit line write potential of the MTJ cell, resulting in 25% of a current that flows from the respective bit line of the MTJ cell, leaking out through the respective bit line of the following MTJ cell, wherein the MTJ and the following MTJ cell are coupled in a string.

10. The method of manufacturing a memory cell array according to claim 1 , wherein a formed MTJ cell in the manufactured memory cell array is further configured to be written to a logic “1” state by:

biasing a respective bit line at a ground potential;

biasing a respective source line at a source line write potential; and

driving a respective word line at a word line write potential.

11. The method of manufacturing a memory cell array according to claim 1 , wherein a formed MTJ cell in the manufactured memory cell array is further configured to be read by:

biasing a respective bit line at a bit line read potential;

biasing a respective source line at a ground potential;

driving a respective word line at a word line read potential; and

sensing a result current on the respective source line.

12. The method of manufacturing a memory cell array according to claim 1 , wherein forming the plurality of bit lines comprises forming each bit line in contact with the planar reference magnetic layer at each level in a periphery region.

13. The method of manufacturing a memory cell array according to claim 12 , further comprising:

selectively removing a portion of the planar reference magnetic layer in the periphery region of a first level to expose the planar reference magnetic layer of a second level formed below the first level; and

forming a first bit line on exposed portions of the planar reference magnetic layer of the first level and a second bit line on exposed portions of the planar reference magnetic layer of the second level in the periphery region.

14. The method of manufacturing a memory cell array according to claim 13 , further comprising:

forming a first global bit line coupled to the first bit line and one or more additional bit lines in a first row; and

forming a second global bit line coupled to the second bit line and one or more additional bit lines in a second row.

Assignments (1)

Continuity (8)