Semiconductor structure with embedded capacitor

1. A semiconductor structure, comprising:

a substrate having a first region, a second region, and a third region;

a capacitor structure disposed in the second region of the substrate, the capacitor structure comprising a capacitor conductor and a dielectric insulator disposed between the capacitor conductor and the substrate;

a stacked device disposed on the first region of the substrate, the stacked device comprising a first transistor and a second transistor in a stacked configuration disposed on the first region of the substrate, the first transistor and the second transistor each being coupled to the capacitor conductor; and

a non-stacked device-disposed on the third region, the non-stacked device comprising a third transistor disposed on the third region and having a gate stack disposed on a top surface thereof and being coupled to the capacitor conductor.

2. The semiconductor structure of claim 1 , wherein the first transistor and the second transistor each being coupled to the capacitor conductor comprises a source/drain region of the first transistor and a source/drain region of the second transistor each being coupled to the capacitor conductor.

3. The semiconductor structure of claim 2 , wherein the source/drain region of the first transistor comprises one of a n-type field effect transistor material and a p-type field effect transistor material and the source/drain region of the second transistor comprises the other of the n-type field effect transistor material and the p-type field effect transistor material.

4. The semiconductor structure of claim 1 , wherein the stacked device comprises a stacked nanosheet device, the first transistor comprising a first nanosheet stack structure of the stacked nanosheet device and the second transistor comprising a second nanosheet stack structure of the stacked nanosheet device, the second nanosheet stack structure being disposed under the first nanosheet stack structure.

5. The semiconductor structure of claim 1 , wherein:

a gate stack of the first transistor comprises a first work function metal;

a gate stack of the second transistor comprises a second work function metal that is different than the first work function metal; and

the gate stack of the third transistor comprises one of the first work function metal and the second work function metal.

6. The semiconductor structure of claim 5 , wherein the gate stack of the third transistor comprises the second work function metal.

7. The semiconductor structure of claim 1 , wherein the stacked device extends from the substrate in a first direction, the at least a portion of the second transistor being disposed below the at least a portion of the first transistor in the first direction.

8. The semiconductor structure of claim 7 , wherein:

the second region comprises a capacitor contact disposed above the capacitor conductor in the first direction; and

the capacitor contact is wider than the capacitor conductor in a second direction that is perpendicular to the first direction.

9. A semiconductor device, comprising:

a nanosheet field-effect transistor device disposed on a semiconductor substrate, wherein the nanosheet field-effect transistor device comprises:

a stacked transistor structure comprising:

a first transistor comprising a first nanosheet stack structure disposed on a first region of the semiconductor substrate; and

a second transistor comprising a second nanosheet stack structure disposed on the first nanosheet stack structure;

a capacitor structure disposed in a second region of the semiconductor substrate; and

a third transistor adjacent the stacked transistor structure, the third transistor comprising a third nanosheet stack structure disposed on a third region of the semiconductor substrate and having a gate stack disposed on a top surface thereof;

wherein the first, second, and third nanosheet stack structures are coupled to the capacitor structure.

10. The semiconductor device of claim 9 , wherein a source/drain region of the first transistor and a source/drain region of the second transistor are coupled to a capacitor conductor of the capacitor structure.

11. The semiconductor device of claim 10 , wherein the source/drain region of the first transistor comprises one of a n-type field effect transistor material and a p-type field effect transistor material and the source/drain region of the second transistor comprises the other of the n-type field effect transistor material and the p-type field effect transistor material.

12. The semiconductor device of claim 9 , wherein:

a gate stack of the first transistor comprises a first work function metal;

a gate stack of the second transistor comprises a second work function metal that is different than the first work function metal; and

the gate stack of the third transistor comprises one of the first work function metal and the second work function metal.

13. The semiconductor device of claim 12 , wherein the gate stack of the third transistor comprises the first work function metal.

14. The semiconductor device of claim 12 , wherein the gate stack of the third transistor is coupled to a capacitor conductor of the capacitor structure.

15. The semiconductor device of claim 9 , wherein the first nanosheet stack structure extends from the semiconductor substrate in a first direction and the second nanosheet stack structure extends from the first nanosheet stack structure in the first direction.

16. The semiconductor device of claim 15 , wherein:

the second region comprises a capacitor contact disposed above a capacitor conductor of the capacitor structure in the first direction; and

the capacitor contact is wider than the capacitor conductor in a second direction that is perpendicular to the first direction.

17. The semiconductor structure of claim 1 , wherein the second region is disposed between the first region and the third region.

18. The semiconductor device of claim 9 , wherein the second region is disposed between the first region and the third region.