Semiconductor device and method for fabricating the same
The present invention provides a highly integrated memory cell and a semiconductor device including the same. According to an embodiment of the present invention, the semiconductor device comprises: a plurality of active layers vertically stacked over a substrate; a plurality of bit lines connected to first ends of the active layers, respectively, and extended parallel to the substrate; line-shape air gaps disposed between the bit lines; a plurality of capacitors connected to second ends of the active layers, respectively; and a word line and a back gate facing each other with each of the active layers interposed therebetween, wherein the word line and the back gate are vertically oriented from the substrate.
1. A semiconductor device, comprising:
a plurality of active layers vertically stacked over a substrate;
a plurality of bit lines connected to first ends of the active layers, respectively, and extended parallel to the substrate;
line-shape air gaps disposed between the bit lines;
a plurality of capacitors connected to second ends of the active layers, respectively;
a word line and a vertical shape air gap facing each other with the active layers interposed therebetween, the word line and the vertical shape air gap are vertically oriented from the substrate; and
a gap capping layer capping an upper surface of the vertical shape air gap.
2. The semiconductor device of claim 1 , wherein the active layers include polysilicon.
3. The semiconductor device of claim 1 ,
wherein the bit lines and the line-shape air gaps alternate in a direction vertical to an upper surface of the substrate.
4. The semiconductor device of claim 1 , wherein each of the active layers comprises:
a channel body disposed between the word line and the vertical shape air gap; and
source/drains on both sides of the channel body,
wherein a thickness of the channel body is smaller than thicknesses of the source/drains.
5. The semiconductor device of claim 4 , wherein the channel body of each of the active layers has a thickness smaller than the word line.
6. The semiconductor device of claim 4 , wherein the channel body of each of the active layers has a thickness of 1 nm to 10 nm.
7. The semiconductor device of claim 1 , further comprising an isolation layer between the active layers, and
wherein the isolation layer is vertically extended from the substrate.
8. The semiconductor device of claim 7 , wherein the word line and the vertical shape air gap penetrate through the isolation layer and vertically extend from the substrate.
9. A method for fabricating a semiconductor device, the method comprising:
forming a mold stack in which insulating layers and sacrificial layers alternate over a substrate;
forming a plurality of isolation layers penetrating through the mold stack;
substituting some of the sacrificial layers between the isolation layers with semiconductor layers;
forming a vertical shape word line and a vertical shape back gate, both vertically penetrating through the isolation layers and facing each other with the semiconductor layers interposed therebetween;
forming bit lines connected to first ends of the semiconductor layers, respectively, and extended parallel to the substrate; and
forming laterally oriented capacitors connected to second ends of the semiconductor layers, respectively.