Optimized contact resistance for stacked FET devices
Stacked FET devices having wrap-around contacts to optimize contact resistance and techniques for formation thereof are provided. In one aspect, a stacked FET device includes: a bottom-level FET(s) on a substrate; lower contact vias present in an ILD disposed over the bottom-level FET(s); a top-level FET(s) present over the lower contact vias; and top-level FET source/drain contacts that wrap-around source/drain regions of the top-level FET(s), wherein the lower contact vias connect the top-level FET source/drain contacts to source/drain regions of the bottom-level FET(s). When not vertically aligned, a local interconnect can be used to connect a given one of the lower contact vias to a given one of the top-level FET source/drain contacts. A method of forming a stacked FET device is also provided.
1. A stacked field-effect transistor (FET) device, comprising:
at least one bottom-level FET on a substrate;
lower contact vias present in an interlayer dielectric (ILD) disposed over the at least one bottom-level FET;
at least one top-level FET present over the lower contact vias; and
top-level FET source/drain contacts that wrap-around source/drain regions of the at least one top-level FET,
wherein the lower contact vias connect the top-level FET source/drain contacts to source/drain regions of the at least one bottom-level FET.
2. The stacked FET device of claim 1 , wherein the top-level FET source/drain contacts are in direct contact with a top and at least one sidewall of the source/drain regions of the at least one top-level FET.
3. The stacked FET device of claim 1 , wherein the top-level FET source/drain contacts are in direct contact with a top, a bottom and at least one sidewall of the source/drain regions of the at least one top-level FET.
4. The stacked FET device of claim 1 , wherein the lower contact vias connect to the top-level FET source/drain contacts from a bottom of the at least one top-level FET.
5. The stacked FET device of claim 1 , wherein a given one of the lower contact vias and a given one of the top-level FET source/drain contacts to which the given lower contact via is connected are unaligned vertically.
6. The stacked FET device of claim 5 , further comprising:
a local interconnect between the given lower contact via and the given top-level FET source/drain contact.
7. The stacked FET device of claim 1 , further comprising:
bottom-level FET source/drain contacts disposed over the source/drain regions of the at least one bottom-level FET.
8. The stacked FET device of claim 7 , wherein the lower contact vias are in direct contact with the bottom-level FET source/drain contacts.
9. The stacked FET device of claim 1 , further comprising:
gates of the at least one top-level FET that are offset from the source/drain regions of the at least one top-level FET by gate spacers, wherein a top surface of the top-level FET source/drain contacts is below a top surface of the gates.
10. The stacked FET device of claim 1 , further comprising:
at least one upper contact via in direct contact with at least one of the lower contact vias.
11. A stacked FET device, comprising:
at least one bottom-level FET on a substrate;
lower contact vias and local interconnects present in an ILD disposed over the at least one bottom-level FET;
at least one top-level FET present over the lower contact vias;
top-level FET source/drain contacts that wrap-around source/drain regions of the at least one top-level FET,
wherein the lower contact vias connect the top-level FET source/drain contacts to source/drain regions of the at least one bottom-level FET, wherein each of the local interconnects connects a given one of the lower contact vias to a given one of the top-level FET source/drain contacts, and wherein each of the top-level FET source/drain contacts is in direct contact with either one of the local interconnects or one of the lower contact vias from a bottom of the at least one top-level FET.
12. The stacked FET device of claim 11 , wherein the top-level FET source/drain contacts are in direct contact with a top and at least one sidewall of the source/drain regions of the at least one top-level FET.
13. The stacked FET device of claim 11 , wherein the top-level FET source/drain contacts are in direct contact with a top, a bottom and at least one sidewall of the source/drain regions of the at least one top-level FET.
14. The stacked FET device of claim 11 , further comprising:
bottom-level FET source/drain contacts disposed over the source/drain regions of the at least one bottom-level FET, wherein the lower contact vias are in direct contact with the bottom-level FET source/drain contacts.