Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes: an N − drift layer of a first conductivity type formed in the semiconductor substrate; a P base layer formed on the N − drift layer; and an N buffer layer of the first conductivity type formed under the N − drift layer and higher in peak impurity concentration than the N − drift layer. The N buffer layer includes: a first buffer layer in which a trap level derived from lattice defect is not detected by a photoluminescence method; and a second buffer layer provided between the first buffer layer and the N − drift layer and in which two types of trap levels derived from lattice defect are detected by the photoluminescence method.
1. A semiconductor device comprising:
a semiconductor substrate with a first main surface and a second main surface;
a drift layer of a first conductivity type formed in the semiconductor substrate;
an impurity diffusion layer of a second conductivity type formed on the drift layer to be closer to the first main surface; and
a buffer layer of the first conductivity type formed on the drift layer to be closer to the second main surface and higher in peak impurity concentration than the drift layer,
the buffer layer comprising:
a first buffer layer absent a lattice defect providing a trap level; and
a second buffer layer provided between the first buffer layer and the drift layer and including a lattice defect providing two types of trap levels.
2. The semiconductor device according to claim 1 , wherein
an insulated gate transistor structure is formed on the impurity diffusion layer to be closer to the first main surface.
3. The semiconductor device according to claim 2 , wherein
a collector layer of the second conductivity type is formed on the buffer layer to be closer to the second main surface.
4. The semiconductor device according to claim 3 , wherein
an active cell region, an edge termination region, and an intermediate region are defined on the semiconductor substrate, the edge termination region being provided external to the active cell region, the intermediate region being located between the active cell region and the edge termination region, and
the buffer layer and the collector layer extend over the active cell region, the intermediate region, and the edge termination region.
5. The semiconductor device according to claim 3 , wherein
an active cell region, an edge termination region, and an intermediate region are defined on the semiconductor substrate, the edge termination region being provided external to the active cell region, the intermediate region being located between the active cell region and the edge termination region,
the buffer layer extends over the active cell region, the intermediate region, and the edge termination region, and
the collector layer is formed only in the active cell region.
6. The semiconductor device according to claim 1 , wherein
the impurity diffusion layer functions as an anode of a diode, and
a cathode layer of the first conductivity type functioning as a cathode of the diode is formed on the buffer layer to be closer to the second main surface.
7. The semiconductor device according to claim 6 , wherein
an active cell region, an edge termination region, and an intermediate region are defined on the semiconductor substrate, the edge termination region being provided external to the active cell region, the intermediate region being located between the active cell region and the edge termination region, and
the buffer layer and the cathode layer extend over the active cell region, the intermediate region, and the edge termination region.
8. The semiconductor device according to claim 1 , wherein
the impurity diffusion layer functions as an anode of a diode, and
a first cathode layer of the first conductivity type and a second cathode layer of the second conductivity type each functioning as a cathode of the diode are formed on the buffer layer to be closer to the second main surface.
9. The semiconductor device according to claim 8 , wherein
an active cell region, an edge termination region, and an intermediate region are defined on the semiconductor substrate, the edge termination region being provided external to the active cell region, the intermediate region being located between the active cell region and the edge termination region,
the buffer layer and the first cathode layer extend over the active cell region, the intermediate region, and the edge termination region, and
the second cathode layer is formed only in the active cell region.
10. The semiconductor device according to claim 1 , wherein
the two types of trap levels provided by the lattice defect in the second buffer layer include Trap A (photon energy: 1.0182 eV) and Trap B (photon energy: 1.0398 eV), and
with photoluminescence (PL) intensity of the Trap B defined as S PLB and PL intensity of the Trap A as S PLA , the ratio of the Trap B in the second buffer layer expressed by the following formula is in a range from 15 to 55%:
Trap B ratio ={ S PLB /( S PLA +S PLB )}×100.
11. The semiconductor device according to claim 10 , wherein
the ratio of the Trap B in a depth direction of the second buffer layer has a distribution that is constantly within a range from 15 to 55%.
12. The semiconductor device according to claim 3 , wherein
a carrier lifetime in the second buffer layer is shorter than respective carrier lifetimes in each of the first buffer layer, the drift layer, and the collector layer.
13. The semiconductor device according to claim 6 , wherein
a carrier lifetime in the second buffer layer is shorter than respective carrier lifetimes in each of the first buffer layer, the drift layer, and the cathode layer.
14. The semiconductor device according to claim 8 , wherein
a carrier lifetime in the second buffer layer is shorter than respective carrier lifetimes in each of the first buffer layer, the drift layer, the first cathode layer, and the second cathode layer.