Dynamic allocation of executable code for multiarchitecture heterogeneous computing

1. An apparatus comprising a plurality of processing units and at least one hardware processor adapted for:

generating a target set of executable instructions using a target block identified in a plurality of blocks of an intermediate representation of a software program, each of the plurality of blocks associated with one of a plurality of execution blocks of the software program and comprising a set of intermediate instructions;

generating a calling set of executable instructions using a calling block identified in the plurality of blocks of the intermediate representation and using at least one computer control instruction for invoking the target set of executable instructions, when the calling set of executable instructions is executed by a calling processing unit and the target set of executable instructions is executed by a target processing unit;

configuring at least one of the calling processing unit and the target processing unit for executing the calling set of executable instructions and the target set of executable instructions, respectively.

2. The apparatus of claim 1 , wherein the at least one hardware processor is further adapted for identifying the calling block and the target block in the plurality of blocks of the intermediate representation of the software program.

3. The apparatus of claim 1 , wherein the target processing unit is further configured for providing the calling processing unit with at least one value produced by the target processing unit executing at least some of the target set of executable instructions.

4. The apparatus of claim 3 , wherein the calling processing unit is further configured for receiving the at least one value, produced by the target processing unit executing at least some of the target set of executable instructions, from the calling processing unit.

5. The apparatus of claim 1 , wherein the calling processing unit is further configured for providing the target processing unit with at least one argument value.

6. The apparatus of claim 1 , wherein the target processing unit is further configured for instructing, after executing at least some other of the target set of executable instructions, the calling processing unit to execute at least some of the calling set of executable instructions.

7. The apparatus of claim 6 , wherein the calling processing unit is further configured for:

suspending execution of the calling set of executable instructions after executing the at least one computer control instruction for invoking the target set of executable instructions; and

executing the at least some of the calling set of executable instructions in response to receiving an instruction from the target processing unit.

8. The apparatus of claim 1 , wherein the target processing unit is selected from a group of processing units consisting of: a central processing unit, a multi-core central processing unit (CPU), a data processing unit (DPU), a microcontroller unit (MCU), an accelerated processing unit (ACU), a field-programmable gate array (FPGA), a coarse-grained reconfigurable architecture (CGRA), a neural-network accelerator, an intelligence processing unit (IPU), an application-specific integrated circuit (ASIC), a quantum computer, and an interconnected computing grid, comprising a plurality of reconfigurable logical elements connected by a plurality of configurable data routing junctions.

9. The apparatus of claim 1 , wherein a first computer architecture of the calling processing unit is different from a second computer architecture of the target processing unit.

10. The apparatus of claim 9 , wherein the calling block comprises at least one control-flow intermediate instruction to execute at least one target intermediate instruction of the target block; and

wherein the calling set of executable instructions comprises a plurality of conversion instructions, implementing an application binary interface applied to the at least one control-flow intermediate instruction to convert between the first computer architecture of the calling processing unit and the second computer architecture of the target processing unit.

11. The apparatus of claim 9 , wherein the target block comprises a plurality of target metadata values; and

wherein generating the target set of executable instructions comprises generating a plurality of converted target metadata values using the plurality of target metadata values according to the second computer architecture of the target processing unit.

12. The apparatus of claim 1 , wherein the calling set of executable instructions comprises at least one first memory access instruction to at least one memory address in an identified range of application memory addresses; and

wherein the target set of executable instructions comprises at least one second memory access instruction to at least one other memory address in the identified range of application memory addresses.

13. The apparatus of claim 12 , wherein the identified range of application memory addresses is one of: a range of physical memory addresses, a range of virtual memory addresses, a range of memory-mapped input-output addresses, and a range of bus addresses.

14. The apparatus of claim 1 , wherein the calling set of executable instructions comprises accessing at least one device using at least one device handle associated with the at least one device; and

wherein the target set of executable instructions comprises accessing the at least one device using the at least one device handle.

15. The apparatus of claim 14 , wherein the at least one device handle is at least one of: a network socket handle, an operating system kernel object handle, and a file descriptor.

16. The apparatus of claim 1 , wherein the at least one hardware processor is further adapted for identifying the calling block and the target block according to a plurality of statistical values collected while at least part of the software program is executed.

17. The apparatus of claim 16 , wherein the at least one hardware processor is further adapted for collecting the plurality of statistical values while executing the at least part of the software program.

18. The apparatus of claim 16 , wherein at least one of the plurality of statistical values is indicative of one of: an outcome of executing a control-flow instruction, a data value of a variable of the software program, a memory access pattern, and a memory virtual address translation.

19. The apparatus of claim 16 , wherein the at least one hardware processor is further adapted for: inserting a plurality of telemetry intermediate instructions into the intermediate representation of the software program, for collecting the plurality of statistical values.

20. The apparatus of claim 1 , wherein the calling processing unit is the at least one hardware processor.

21. A method for executing a software program, comprising:

generating a target set of executable instructions using a target block identified in a plurality of blocks of an intermediate representation of a software program, each of the plurality of blocks associated with one of a plurality of execution blocks of the software program and comprising a set of intermediate instructions;

generating a calling set of executable instructions using a calling block identified in the plurality of blocks of the intermediate representation and using at least one computer control instruction for invoking the target set of executable instructions, when the calling set of executable instructions is executed by a calling processing unit and the target set of executable instructions is executed by a target processing unit; and

configuring at least one of the calling processing unit and the target processing unit for executing the calling set of executable instructions and the target set of executable instructions, respectively.

22. A software program product for executing a software program, comprising:

a non-transitory computer readable storage medium;

first program instructions for: generating a target set of executable instructions using a target block identified in a plurality of blocks of an intermediate representation of a software program, each of the plurality of blocks associated with one of a plurality of execution blocks of the software program and comprising a set of intermediate instructions; and

second program instructions for: generating a calling set of executable instructions using a calling block identified in the plurality of blocks of the intermediate representation and using at least one computer control instruction for invoking the target set of executable instructions, when the calling set of executable instructions is executed by a calling processing unit and the target set of executable instructions is executed by a target processing unit; and

third program instructions for: configuring at least one of the calling processing unit and the target processing unit for executing the calling set of executable instructions and the target set of executable instructions, respectively;

wherein the first, second, and third program instructions are executed by at least one computerized processor from the non-transitory computer readable storage medium.