Flash memory structure with enhanced floating gate

1. A method of forming a flash memory structure, comprising:

forming a sacrificial material over a substrate;

removing a part of the sacrificial material to form a plurality of trenches extending through the sacrificial material to within the substrate;

forming a dielectric material within the plurality of trenches;

selectively etching the dielectric material, according to a mask that is directly over the dielectric material, to form depressions along edges of the plurality of trenches, wherein the mask has a width that increases as a distance from the substrate increases;

removing the sacrificial material from between neighboring ones of the depressions to form a floating gate recess; and

forming a floating gate material within the floating gate recess and the neighboring ones of the depressions.

2. The method of claim 1 , wherein opposing sides of respective ones of the plurality of trenches are formed by sidewalls of the sacrificial material.

3. The method of claim 1 , further comprising:

forming the mask over a top surface of the dielectric material and directly between sidewalls of the dielectric material; and

completely removing the mask from over the top surface of the dielectric material, while leaving the mask directly between the sidewalls of the dielectric material.

4. The method of claim 1 , wherein the part of the sacrificial material is removed prior to forming the dielectric material within the plurality of trenches.

5. The method of claim 1 , wherein the depressions respectively have a first side defined by a sidewall of the dielectric material, and an opposing second side defined by a sidewall of the substrate and a sidewall of the sacrificial material.

6. The method of claim 1 , further comprising:

performing a planarization process after forming the floating gate material within the floating gate recess, wherein the planarization process causes an upper surface of the dielectric material to be substantially co-planar with an upper surface of the floating gate material.

7. The method of claim 6 , further comprising:

etching the dielectric material, after forming the floating gate material within the floating gate recess, to recess the dielectric material below the upper surface of the floating gate material.

8. A method of forming a flash memory structure, comprising:

forming a sacrificial material over an upper surface of a substrate;

forming trenches extending through the sacrificial material to within the substrate;

forming a dielectric material within the trenches and over the sacrificial material, the dielectric material having a recess directly over the trenches;

forming a masking layer over the dielectric material and within the recess;

performing a first etching process to etch areas of the dielectric material that are outside of the masking layer, the first etching process exposing sidewalls of the sacrificial material and removing a part of the dielectric material from below the upper surface of the substrate;

performing a second etching process on the sacrificial material to form a floating gate recess; and

forming a floating gate material within the floating gate recess.

9. The method of claim 8 , wherein the floating gate material is formed onto an upper surface of the dielectric material that is within the trenches.

10. The method of claim 8 , wherein the masking layer completely fills the recess.

11. The method of claim 8 ,

wherein a top of the dielectric material is completely confined below the masking layer; and

wherein the dielectric material extends laterally past opposing outermost edges of the masking layer.

12. The method of claim 8 , further comprising:

forming the masking layer over the dielectric material and directly between sidewalls of the dielectric material; and

performing a planarization process to remove a part of the masking layer and to expose upper surfaces of the sacrificial material, the dielectric material, and the masking layer.

13. A method of forming a flash memory structure, comprising:

forming a first trench and a second trench within a semiconductor substrate;

forming a dielectric material within the first trench and the second trench;

forming a mask over the dielectric material;

performing a planarization process to remove a part of the mask and expose an upper surface of the dielectric material; and

patterning the dielectric material so that the dielectric material within the first trench is at least partially separated from the semiconductor substrate by a first recess and so that the dielectric material within the second trench is at least partially separated from the semiconductor substrate by a second recess, wherein the dielectric material is patterned by etching the upper surface of the dielectric material that was exposed by the planarization process to define the first recess and the second recess; and

forming a floating gate that continuously extends from within the first recess to within the second recess.

14. The method of claim 13 , wherein the floating gate is formed directly between a sidewall of the dielectric material and a sidewall of the semiconductor substrate.

15. The method of claim 13 ,

wherein the floating gate has a first lower surface that faces the semiconductor substrate and that is above an upper surface of the semiconductor substrate that is between the first trench and the second trench; and

wherein the floating gate has a second lower surface that faces the semiconductor substrate and that is below the upper surface of the semiconductor substrate.

16. The method of claim 13 , wherein the mask has an uppermost surface that continuously extends between outermost edges of the mask.

17. The method of claim 13 , wherein an uppermost surface of the mask is substantially co-planar with an uppermost surface of the dielectric material.

18. The method of claim 13 , further comprising:

forming a source region and a drain region within the semiconductor substrate, wherein the floating gate is formed between the source region and the drain region;

forming a second dielectric material over the floating gate;

forming a control gate over the second dielectric material; and

forming a select gate over the semiconductor substrate and laterally between the source region and the floating gate.

19. The method of claim 13 , wherein the mask has a tapered profile after performing the planarization process, as viewed along a cross-sectional view.

20. The method of claim 13 , wherein the mask comprises polysilicon.