Packaging substrate and semiconductor apparatus comprising same

1. A semiconductor apparatus comprising:

a semiconductor element unit comprising one or more semiconductor elements;

a packaging substrate, connected to the semiconductor elements, comprising a core layer and an upper layer disposed on the core layer, the core layer comprising a glass substrate, a core via, and a core distribution layer disposed on a surface of the glass substrate or a surface of the core via, the glass substrate having a first surface and a second surface facing each other; and

a motherboard electrically connected to the packaging substrate and configured to transmit electrical signals to the one or more semiconductor elements and to connect the semiconductor elements,

wherein the core via penetrates through the glass substrate in a thickness direction in a plural number,

wherein at least a part of the core distribution layer connects electrically conductive layers of the first surface and an electrically conductive layer of the second surface through the core via penetrating through the glass substrate,

wherein the upper layer is disposed on the first surface and comprises an electrically conductive layer connecting the core distribution layer and an external semiconductor element unit, and

wherein a thickness of a thinnest layer among the electrically conductive layers of the core distribution layer is the same as or greater than a width of a thinnest layer among the electrically conductive layers of the upper layer.

2. The semiconductor apparatus of claim 1 ,

wherein the thickness of the thinnest layer among the electrically conductive layers of the core distribution layer is greater than the width of the thinnest layer among the electrically conductive layers of the upper layer by 1 to 12 times.

3. The semiconductor apparatus of claim 1 , further comprising:

an upper insulating layer and an upper distribution pattern,

wherein the upper insulating layer is disposed on the first surface,

the upper distribution pattern at least partially comprising a fine pattern is at least partially connected to the core distribution layer,

the upper distribution pattern is an electrically conductive layer embedded in the upper insulating layer, and

the fine pattern has a width of less than 4 μm with an interval of less than 4 μm.

4. The semiconductor apparatus of claim 1 ,

wherein the core distribution layer comprises a core distribution pattern comprising a second surface distribution pattern,

wherein the second surface distribution layer is an electrically conductive layer disposed on the second surface, and

wherein a width of an electrically conductive layer having a greatest width within the second surface distribution pattern is 1 to 20 times of a width of a thinnest layer among the electrically conductive layers of the upper layer.

5. A packaging substrate comprising:

a core layer and an upper layer disposed on the core layer, the core layer comprising a glass substrate, a core via, and a core distribution layer disposed on a surface of the glass substrate or a surface of the core via, the glass substrate having a first surface and a second surface facing each other,

wherein the core via penetrates through the glass substrate in a thickness direction in a plural number,

wherein at least a part of the core distribution layer connects an electrically conductive layer of the first surface and an electrically conductive layer of the second surface through the core via penetrating through the glass substrate,

wherein the upper layer is disposed on the first surface and comprises an electrically conductive layer connecting the core distribution layer and an external semiconductor element unit, and

wherein a thickness of a thinnest layer among electrically conductive layers of the core distribution layer is the same as or greater than a width of a thinnest layer among the electrically conductive layers of the upper layer.

6. A semiconductor apparatus comprising:

a semiconductor element unit comprising one or more semiconductor elements;

a packaging substrate, connected to the semiconductor elements, comprising a core layer and an upper layer disposed on the core layer, the core layer comprising a glass substrate, a core via, and a core distribution layer disposed on a surface of the glass substrate or a surface of the core via, the glass substrate having a first surface and a second surface facing each other; and

a motherboard connected to the packaging substrate, and configured to transmit electrical signals to the one or more semiconductor elements and to connect the semiconductor elements,

wherein the core via penetrates through the glass substrate in a thickness direction in a plural number,

wherein at least a part of the core distribution layer connects an electrically conductive layer of the first surface and an electrically conductive layer of the second surface through the core vias,

wherein the upper layer is disposed on the first surface and comprises an electrically conductive layer connecting the core distribution layer and an external semiconductor element unit, and

wherein a thickness of a thinnest layer among electrically conductive layers of the core distribution layer is the same as or greater than a thickness of a thinnest layer among the electrically conductive layers of the upper layer.

7. The semiconductor apparatus of claim 6 ,

wherein the thickness of the thinnest layer among the electrically conductive layers of the core distribution layer is greater than the thickness of the thinnest layer among the electrically conductive layers of the upper layer by 0.7 to 12 times.

8. The semiconductor apparatus of claim 6 , further comprising:

an upper insulating layer and an upper distribution pattern,

wherein the upper insulating layer is disposed on the first surface,

the upper distribution pattern at least partially comprising a fine pattern is at least partially connected to the core distribution layer,

the upper distribution pattern is an electrically conductive layer embedded in the upper insulating layer, and

the fine pattern has a width of less than 4 μm with an interval of less than 4 μm.

9. The semiconductor apparatus of claim 6 ,

wherein the core distribution layer comprises a core distribution pattern comprising a second surface distribution pattern,

wherein the second surface distribution layer is an electrically conductive layer disposed on the second surface, and

wherein a thickness of an electrically conductive layer having a greatest thickness among the second surface distribution pattern is 0.7 to 20 times of the thickness of a thinnest layer among the electrically conductive layers of the upper layer.

10. A packaging substrate comprising:

a core layer and an upper layer disposed on the core layer,

the core layer comprising a glass substrate, a core via, and a core distribution layer disposed on a surface of the glass substrate or a surface of the core via, the glass substrate having a first surface and a second surface facing each other,

wherein the core via penetrates through the glass substrate in a thickness direction in a plural number,

wherein at least a part of the core distribution layer connects an electrically conductive layer of the first surface and an electrically conductive layer of the second surface through the core via penetrating through the glass substrate,

wherein the upper layer is disposed on the first surface and comprises an electrically conductive layer connecting the core distribution layer and an external semiconductor element unit, and

wherein a thickness of a thinnest layer among electrically conductive layers of the core distribution layer is the same as or greater than a thickness of a thinnest layer among the electrically conductive layers of the upper layer.