Integrated circuit device
An integrated circuit device includes a substrate; an integrated circuit area disposed on the substrate and comprising a dielectric stack; a seal ring disposed in the dielectric stack and around a periphery of the integrated circuit area; a cap layer on the dielectric stack; a trench around the seal ring and exposing a sidewall of the dielectric stack; a memory storage structure disposed on the cap layer; and a moisture blocking layer continuously covering the integrated circuit area and the memory storage structure. The moisture blocking layer extends to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.
1. An integrated circuit device, comprising:
a substrate;
an integrated circuit area on the substrate, said integrated circuit area comprising a dielectric stack;
a seal ring disposed in said dielectric stack and around a periphery of said integrated circuit area;
a cap layer on the dielectric stack;
a trench around the seal ring and exposing a sidewall of said dielectric stack;
a memory storage structure disposed on said cap layer; and
a moisture blocking layer continuously covering said integrated circuit area and said memory storage structure, wherein said moisture blocking layer extends to said sidewall of said dielectric stack, thereby sealing a boundary between two adjacent dielectric films in said dielectric stack.
2. The integrated circuit device according to claim 1 , wherein said substrate is a silicon-on-insulator (SOI) substrate comprising a lower substrate, a buried oxide layer on the lower substrate, and a device layer on the buried oxide layer.
3. The integrated circuit device according to claim 2 , wherein said device layer comprises a silicon layer.
4. The integrated circuit device according to claim 2 , wherein said seal ring is electrically coupled to said lower substrate with a through contact that penetrates through said device layer and said buried oxide layer.
5. The integrated circuit device according to claim 1 , wherein said two adjacent dielectric films are two adjacent low-dielectric constant (low-k) dielectric films.
6. The integrated circuit device according to claim 1 , wherein said seal ring is a discontinuous seal ring.
7. The integrated circuit device according to claim 6 , wherein said seal ring is composed of interconnected metal lines and vias.
8. The integrated circuit device according to claim 7 , wherein said metal lines comprise a topmost copper metal layer.
9. The integrated circuit device according to claim 8 , wherein said topmost copper metal layer is a topmost damascene copper layer.
10. The integrated circuit device according to claim 9 further comprising:
a topmost inter-layer dielectric (ILD) film covering said moisture blocking layer and said MIM capacitor;
a topmost via layer penetrating through said topmost ILD film and said moisture blocking layer to electrically connect with said topmost copper metal layer; and
an aluminum pad disposed on and electrically connected to said topmost via layer.
11. The integrated circuit device according to claim 10 further comprising:
a passivation layer covering a periphery of said aluminum pad and a top surface of said topmost ILD film.
12. The integrated circuit device according to claim 11 , wherein said topmost ILD film comprises silicon oxide.
13. The integrated circuit device according to claim 11 , wherein said passivation layer comprises polyimide or silicon oxide.
14. The integrated circuit device according to claim 1 , wherein said moisture blocking layer comprises silicon nitride, silicon oxynitride, or silicon carbonitride.
15. The integrated circuit device according to claim 1 , wherein said memory storage structure is a data storage structure of a magneto-resistive random access memory (MRAM) device, a resistive RAM (RRAM) or a phase-change memory (PCM).