IP Library Granted Patent US 12,470,518
Granted Patent B2
US 12,470,518 · App. 17/409,540 · Granted Nov 11, 2025

Physically distributed control plane firewalls with unified software view

Inventors: Jyotirmaya Swain (Bangalore, IN); Padam Krishnani (Bangalore, IN); Swapnil Tapadia (Bangalore, IN); Harshil Jain (Udaipur, IN)
Assignee: NVIDIA CORPORATION
H04L63/0236G06F12/0646G06F13/4027H04L63/0218G06F2212/1008
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Quick Facts
Patent No.
US 12,470,518
App. No.
17/409,540
Granted
Nov 11, 2025
Kind
B2
Abstract

Various embodiments include techniques for processing transactions via a computer system interconnect with a distributed firewall. The distributed firewall includes separate firewalls for various initiators of transactions and separate firewalls for various targets of those transactions. As a result, transactions proceed, for example, along the shortest path from the initiator to the target, rather than being routed through a centralized firewall. In addition, firewall transactions, for example, may be remapped such that initiators address the initiator firewalls and target firewalls via a unified address space, without having to maintain separate base addresses for each initiator firewall and target firewall. As a result, application programs, for example, can execute transactions with increased performance on a computer system as compared to prior approaches.

Claims (48)

1 . A computer-implemented method for processing a first transaction via an interconnect comprising a two-dimensional mesh network, the method comprising:

receiving the first transaction from an initiator via a first node included in the two-dimensional mesh network;

determining that the first transaction is directed at a first firewall;

suspending execution of the first transaction;

generating a map that merges memory address spaces of a plurality of firewalls including the first firewall into a unified memory address space that has a single firewall base address for all firewalls included in the plurality of firewalls, wherein each firewall included in the plurality of firewalls is addressed by adding the single firewall base address to an offset that is different for each firewall included in the plurality of firewalls;

modifying, via the map, a memory address included in the first transaction and in a first memory address format in a memory address space of the first firewall to generate a modified memory address in a second memory address format in the unified memory address space; and

transmitting, via a second node included in the two-dimensional mesh network, the first transaction including the modified memory address to a target coupled to the first firewall.

2 . The computer-implemented method of claim 1 , wherein:

the first firewall comprises an initiator firewall that performs a first authorization function on a second transaction, and

a second firewall comprising a target firewall performs a second authorization function on the second transaction.

3 . The computer-implemented method of claim 2 , wherein the first authorization function comprises determining that an initiator associated with the initiator firewall is authorized to direct the second transaction towards a memory address space that includes a second memory address included in the second transaction.

4 . The computer-implemented method of claim 2 , wherein the second authorization function comprises determining that whether an initiator associated with the initiator firewall is authorized to direct the second transaction towards a target protected by the target firewall.

5 . The computer-implemented method of claim 1 , further comprising, subsequent to suspending the execution of the first transaction, forwarding the first transaction to a firewall remapper.

6 . The computer-implemented method of claim 1 , further comprising, subsequent to modifying the memory address included in the first transaction to generate the modified memory address, forwarding the first transaction to an address space associated with the modified memory address.

7 . The computer-implemented method of claim 1 , wherein the first firewall comprises an initiator firewall and a target firewall, and further comprising:

determining a path between an initiator and at least one of the initiator firewall or the target firewall through a plurality of nodes included in the interconnect; and

transmitting the first transaction from the initiator to the at least one of the initiator firewall or the target firewall via the path.

8 . The computer-implemented method of claim 1 , wherein the first memory address format comprises:

a base address of a firewall address space that includes a plurality of address spaces corresponding to a plurality of firewalls that includes the first firewall; and

an offset associated with the first firewall.

9 . The computer-implemented method of claim 1 , wherein the second memory address format comprises:

a base address of a firewall address space that corresponds to the first firewall; and

an offset associated with the first firewall.

10 . The computer-implemented method of claim 1 , wherein the first firewall comprises an initiator firewall that is configured to perform authorization functions for a plurality of initiators.

11 . The computer-implemented method of claim 1 , wherein the first firewall comprises a target firewall that is configured to perform authorization functions for a plurality of targets.

12 . The computer-implemented method of claim 1 , wherein the first firewall comprises an initiator firewall that is coupled to a first node included in a plurality of nodes within the interconnect, and a second firewall comprises a target firewall that is coupled to the first node.

13 . The computer-implemented method of claim 1 , wherein the first firewall comprises an initiator firewall that is coupled to a first node included in a plurality of nodes within the interconnect, and a second firewall comprises a target firewall that is coupled to a second node included in the plurality of nodes.

14 . A system, comprising:

an initiator firewall comprising a first microprocessor executing instructions stored in a first memory;

a target firewall comprising a second microprocessor executing instructions stored in a second memory;

a firewall trap that:

receives a first transaction from an initiator coupled to the initiator firewall via a first node included in a two-dimensional mesh network;

determines that a first transaction is directed at the initiator firewall or the target firewall, and

suspends execution of the first transaction;

a firewall remapper that:

generates a map that merges memory address spaces of a plurality of firewalls including the initiator firewall and the target firewall into a unified memory address space that has a single firewall base address for all firewalls included in the plurality of firewalls, wherein each firewall included in the plurality of firewalls is addressed by adding the single firewall base address to an offset that is different for each firewall included in the plurality of firewalls, and

modifies, via the map, a memory address included in the first transaction and in a first memory address format in a memory address space of the initiator firewall or the target firewall to generate a modified memory address in a second memory address format in the unified memory address space; and

an interconnect comprising a two-dimensional mesh network that transmits, via a second node included in the two-dimensional mesh network, the first transaction including the modified memory address to the initiator coupled to the initiator firewall or a target coupled to the target firewall.

15 . The system of claim 14 , wherein:

the initiator firewall performs a first authorization function on a second transaction, and

the target firewall performs a second authorization function on the second transaction.

16 . The system of claim 15 , wherein the first authorization function comprises determining that an initiator associated with the initiator firewall is authorized to direct the second transaction towards a memory address space that includes a second memory address included in the second transaction.

17 . The system of claim 15 , wherein the second authorization function comprises determining that whether an initiator associated with the initiator firewall is authorized to direct the second transaction towards a target protected by the target firewall.

18 . The system of claim 14 , wherein, subsequent to suspending execution of the first transaction, the firewall trap further forwards the first transaction to the firewall remapper.

19 . The system of claim 14 , wherein, subsequent to the firewall remapper modifying the memory address included in the first transaction to generate the modified memory address, the firewall trap further forwards the first transaction to an address space associated with the modified memory address.

20 . The system of claim 14 , wherein the system further comprises an initiator associated with the initiator firewall and a target associated with the target firewall, and wherein the interconnect further:

determines a path between the initiator and the target through a plurality of nodes included in the interconnect; and

transmits a second transaction from the initiator to the target via the path.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2021
From: SWAIN, JYOTIRMAYA; KRISHNANI, PADAM; TAPADIA, SWAPNIL; JAIN, HARSHIL
To: NVIDIA CORPORATION
Reel/Frame 057302/0812 →
Continuity (1)
Related Publication 20230057698A1 · Feb 23, 2023
References Cited (40)
US 5734847A · Garbus · 1998 [cited by examiner]
US 6425023B1 · Batchelor · 2002 [cited by examiner]
US 6629157B1 · Falardeau · 2003 [cited by examiner]
US 8850098B2 · Madukkarumukumana · 2014 [cited by examiner]
US 9747219B1 · Bashari · 2017 [cited by examiner]
US 10013388B1 · Wang · 2018 [cited by examiner]
US 10608640B1 · Orthner · 2020 [cited by examiner]
US 10740265B1 · Xu · 2020 [cited by examiner]
US 11074206B1 · Jalal · 2021 [cited by examiner]
US 11899604B2 · Markovic · 2024 [cited by examiner]
US 12007892B2 · Stabrawa · 2024 [cited by examiner]
US 20030135685A1 · Cowan · 2003 [cited by examiner]
US 20070079044A1 · Mandal · 2007 [cited by examiner]
US 20070226795A1 · Conti · 2007 [cited by examiner]
US 20080082622A1 · Pong · 2008 [cited by examiner]
US 20080163353A1 · Conti · 2008 [cited by examiner]
US 20080163358A1 · Conti · 2008 [cited by examiner]
US 20080209099A1 · Kloeppner · 2008 [cited by examiner]
US 20110072246A1 · Yamada · 2011 [cited by examiner]
US 20140122828A1 · Kagan · 2014 [cited by examiner]
US 20140237156A1 · Regula · 2014 [cited by examiner]
US 20150120969A1 · He · 2015 [cited by examiner]
US 20150261709A1 · Billi · 2015 [cited by examiner]
US 20150281126A1 · Regula · 2015 [cited by examiner]
US 20150293873A1 · Shao · 2015 [cited by examiner]
US 20160085684A1 · Borikar · 2016 [cited by examiner]
US 20160154756A1 · Dodson · 2016 [cited by examiner]
US 20160283399A1 · Das Sharma · 2016 [cited by examiner]
US 20170286314A1 · Shacham · 2017 [cited by examiner]
US 20180189057A1 · Werner · 2018 [cited by examiner]
US 20180322082A1 · Breakstone · 2018 [cited by examiner]
US 20190013965A1 · Sindhu · 2019 [cited by examiner]
US 20190180183A1 · Diamant · 2019 [cited by examiner]
US 20190236038A1 · Choudhary · 2019 [cited by examiner]
US 20190364018A1 · Mundra · 2019 [cited by examiner]
US 20200081858A1 · Philmore · 2020 [cited by examiner]
US 20200336337A1 · Williams · 2020 [cited by examiner]
US 20210334023A1 · Lossin · 2021 [cited by examiner]
Tu et al.; Seamless Fail-over for PCIe Switched Networks; 2018; retrieved from the Internet https://dl.acm.org/doi/abs/10.1145/3211890.3211895; pp. 1-11, as printed. (Year: 2018). [cited by examiner]
First Office Action received for Chinese Application No. 202210691217.6, dated Jun. 21, 2025, 30 pages. [cited by applicant]