Methods for passivating sidewalls of semiconductor wafers and semiconductor devices incorporating semiconductor wafers
A method for passivating sidewalls of patterned semiconductor wafer including ridge(s). The method includes: depositing first layer of first dielectric material on pattern surface of said wafer; etching portion of first layer to obtain tapered portions of first dielectric material along sidewall(s) of ridge(s); depositing second layer of second dielectric material on tapered portions and said wafer; depositing photo-sensitive material on second layer; aligning mask with photo-sensitive material, wherein portion(s) of photo-sensitive material corresponding to top surface of ridge(s) is/are unmasked, and remaining portion is masked; applying developing solution and exposing photo-sensitive material to remove portion(s) of photo-sensitive material; etching portion(s) of second layer that is/are deposited on top surface of ridge(s); and removing photo-sensitive material.
1. A method for passivating sidewalls of a patterned semiconductor wafer comprising at least one ridge, the method comprising:
depositing a first layer of a first dielectric material on a pattern surface of the patterned semiconductor wafer;
etching a portion of the first layer to remove the first layer from a top surface of the at least one ridge and obtain tapered portions of the first dielectric material along at least one sidewall of the at least one ridge;
depositing a second layer of a second dielectric material on the tapered portions and the patterned semiconductor wafer, wherein the top surface of the at least one ridge is covered only by the second layer;
depositing a photo-sensitive material on the second layer;
aligning a mask with the photo-sensitive material, wherein at least one portion of the photo-sensitive material corresponding to a top surface of the at least one ridge is unmasked, and a remaining portion of the photo-sensitive material is masked;
applying a developing solution on the photo-sensitive material and exposing the photo-sensitive material to a light source, to remove the at least one portion of the photo-sensitive material and leave only the second layer covering the top surface of the at least one ridge;
etching at least one portion of the second layer that is covering the top surface of the at least one ridge to expose at least one portion of the top surface of the at least one ridge; and
removing the photo-sensitive material, wherein the passivated sidewalls comprise the first layer covered by the second layer, wherein a thickness of the first layer is in a range of 400 to 2000 nanometers and a thickness of the second layer is in a range of 200-1000 nanometers.
2. The method according to claim 1 , wherein the step of etching the portion of the first layer is performed by employing a Reactive-Ion Etching (RIE) process.
3. The method according to claim 2 , wherein the RIE process is performed anisotropically to obtain a tapered profile of a given tapered portion, wherein a thickness of the given tapered portion is maximum at a bottom end of the at least one sidewall and reduces on going from the bottom end towards a top end of the at least one sidewall.
4. The method according to claim 3 , wherein an extent of tapering in the tapered profile depends on an ion bombardment angle.
5. The method according to claim 1 , wherein the thickness of the second layer is lesser than the thickness of the first layer.
6. The method according to claim 1 , further comprising depositing a metallic layer on a pattern surface of the patterned semiconductor wafer to form a first electrode, using a metallization process.
7. The method according to claim 1 , further comprising fabricating the at least one ridge on the patterned semiconductor wafer by employing at least one epitaxial process.
8. The method according to claim 1 , wherein the step of depositing the first layer of the first dielectric material or the step of depositing the second layer of the second dielectric material is performed by employing a Plasma-Enhanced Chemical Vapor Deposition (PECVD) process.
9. The method according to claim 1 , wherein the step of depositing the photo-sensitive material is performed by employing a spin coating process.
10. The method according to claim 1 , wherein the first layer of the first dielectric material or the second layer of the second dielectric material is one of: silicon dioxide (SO2), silicon oxynitride (SiOxNy), silicon nitride (Si3N4).
11. The method according to claim 1 , wherein the thickness of the first layer is in the range of 500 nanometers to 1200 nanometers and the thickness of the second layer is in the range of 200-nanometers to 600 nanometers.