Multi-input downconversion mixer
Multi-input downconversion mixers, systems, and methods are provided with input switching in the intermediate frequency or baseband domain. One illustrative mixer embodiment includes: multiple differential pairs of transistors and multiple pairs of switches. Each differential transistor pair has their bases or gates driven by a differential reference signal, their emitters or sources connected to a common node having a current or voltage driven based on a respective one of multiple receive signals, and their collectors or drains providing a product of the differential reference signal with the respective one of the multiple receive signals. Each of the switch pairs selectively couples differential output nodes to the collectors or drains of a respective one of the multiple differential pairs, enabling the differential output nodes to convey an output signal that is a sum of products from selected ones of the multiple differential pairs.
1. A multi-input downconversion mixer that comprises:
multiple differential pairs of transistors, each pair having their bases or gates driven by a differential reference signal, having their emitters or sources connected to a common node having a current or voltage driven based on a respective one of multiple radio frequency (RF) signals, and having their collectors or drains each providing a corresponding differential intermediate frequency (IF) signal;
differential output nodes; and
multiple pairs of switches, each pair selectively connecting a respective one of the differential IF signals to the differential output nodes thereby forming a sum of the selectively connected differential IF signals.
2. The mixer of claim 1 , wherein at least one of the multiple differential pairs of transistors is driven with a differential reference signal having an opposite polarity of the differential reference signal driving another of the multiple differential pairs of transistors, causing said sum to represent a difference between corresponding ones of the multiple RF signals.
3. The mixer of claim 1 , further comprising:
capacitors coupled to the differential output nodes to suppress frequencies of the multiple RF signals; and
load impedances to bias the differential output nodes.
4. The mixer of claim 1 , further comprising: multiple load impedances, each load impedance biasing the common node of a respective one of the differential pairs.
5. The mixer of claim 4 , wherein the multiple load impedances are each part of a corresponding voltage divider coupled between a reference voltage and the common node of a respective one of the multiple differential pairs, the respective one of the multiple receive signals driving an intermediate node of the corresponding voltage divider.
6. The mixer of claim 1 , further comprising: multiple input transistors each coupled between a reference voltage and the common node of a respective one of the multiple differential pairs, and each having a base or gate driven by a respective one of the multiple receive signals.
7. The mixer of claim 1 , wherein a differential antenna signal forms two of the multiple receive signals.
8. The mixer of claim 1 , wherein the multiple pairs of switches each comprise a pair of field effect transistors.
9. A multi-input downconversion method that comprises:
supplying a differential reference signal to the bases of each of multiple differential pairs of transistors, each of the multiple differential pairs having their emitters connected to a common node;
driving a current from each of the common nodes based on a respective one of multiple radio frequency (RF) signals to produce a corresponding differential intermediate frequency (IF) signal; and
using multiple pairs of switches to selectively connect the differential IF signals to a pair of differential output nodes to sum the selectively connected differential IF signals.
10. The method of claim 9 , wherein the differential reference signal is supplied to the bases of at least one of the multiple differential pairs with a polarity opposite that of the differential signal supplied to the bases of at least one other of the multiple differential pairs, thereby cause the sum to represent a difference between corresponding ones of the multiple RF signals.
11. The method of claim 9 , further comprising: suppressing high frequencies from the output signal, said high frequencies including those of the differential reference signal and the multiple receive signals.
12. The method of claim 9 , further comprising: biasing the differential output nodes with load impedances.
13. The method of claim 9 , further comprising: biasing the common node of each of the differential pairs with respective load impedances.
14. The method of claim 9 , wherein said driving employs voltage dividers coupled between a reference voltage and the common nodes of the multiple differential pairs.
15. The method of claim 9 , wherein said driving employs input transistors each coupled between a reference voltage and the common node of a respective one of the multiple differential pairs, and each having a base or gate driven by a respective one of the multiple receive signals.
16. The method of claim 9 , wherein a differential antenna signal forms two of the multiple receive signals.
17. The method of claim 9 , wherein the multiple pairs of switches each comprise a pair of field effect transistors.