IP Library › Granted Patent US 11,943,943
Granted Patent B2
US 11,943,943 · App. 17/411,268 · Granted Mar 26, 2024

Detection device

Inventor: Yasushi Kawata (Tokyo, JP)
Assignee: Japan Display Inc.
H10K39/32G06V40/1318H10K19/20H10K30/40H10K30/81H10K30/451
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Quick Facts
Patent No.
US 11,943,943
App. No.
17/411,268
Granted
Mar 26, 2024
Kind
B2
Abstract

A detection device includes a substrate, a plurality of detection electrodes arranged in a detection area of the substrate, an organic semiconductor layer that covers the detection electrodes, and a counter electrode provided above the organic semiconductor layer. The organic semiconductor layer includes at least either of a first p-type semiconductor layer and a first n-type semiconductor layer, and an active layer. The active layer is provided in each overlapping area overlapping a corresponding one of the detection electrodes, and has a structure in which a p-type semiconductor area and an n-type semiconductor area are mixed and coexist. The first p-type semiconductor layer or the first n-type semiconductor layer is provided in a non-overlapping area not overlapping the detection electrode, and is provided between the adjacent active layers.

Claims (20)

1. A detection device comprising:

a substrate;

a plurality of detection electrodes arranged in a detection area of the substrate;

an organic semiconductor layer covering the detection electrodes;

a counter electrode provided above the organic semiconductor layer; and

a plurality of first buffer layers,

wherein

the organic semiconductor layer includes at least either of a first p-type semiconductor layer and a first n-type semiconductor layer, and an active layer,

the active layer is provided in each overlapping area overlapping a corresponding one of the detection electrodes, and has a structure in which a p-type semiconductor and an n-type semiconductor are mixed and coexist,

the first p-type semiconductor layer or the first n-type semiconductor layer is provided in a non-overlapping area not overlapping the detection electrode, and is provided between the adjacent active layers,

the first buffer layers are provided between the active layers and the detection electrodes, and are provided so as to be separated from one another on a per detection electrode basis, and

the first buffer layers each include a plurality of zinc oxide nanoparticles and a zinc acetate layer provided in a space among the zinc oxide nanoparticles.

2. The detection device according to claim 1 , further comprising a second p-type semiconductor layer and a second buffer layer between the active layer and the counter electrode, the second p-type semiconductor layer and the first second buffer layer being disposed over the overlapping area and the non-overlapping area, wherein

in the non-overlapping area, the first p-type semiconductor layer and the second p-type semiconductor layer are stacked so as to contact each other in a direction orthogonal to the substrate.

3. The detection device according to claim 1 , further comprising a second n-type semiconductor layer and a first second buffer layer between the active layer and the counter electrode, the second n-type semiconductor layer and the second buffer layer being disposed over the overlapping area and the non-overlapping area, wherein

in the non-overlapping area, the first n-type semiconductor layer and the second n-type semiconductor layer are stacked so as to contact each other in a direction orthogonal to the substrate.

4. The detection device according to claim 1 , wherein a ratio of the p-type semiconductor to the n-type semiconductor in the overlapping area varies in a direction orthogonal to the substrate.

5. The detection device according to claim 1 , wherein at least either of the first p-type semiconductor layer and the first n-type semiconductor layer is provided between the adjacent detection electrodes.

6. The detection device according to claim 1 , comprising an array substrate in which the substrate, a plurality of switching elements provided for the respective detection electrodes on the substrate, a plurality of gate lines, a plurality of signal lines, and a planarization layer covering the switching elements, the gate lines, and the signal lines are included, wherein

the detection electrodes, the organic semiconductor layer, and the counter electrode are provided above the planarization layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2021
From: KAWATA, YASUSHI
To: JAPAN DISPLAY INC.
Reel/Frame 057286/0868 →
Priority Claims (2)
JP 2019-052564 · Mar 20, 2019 · national
JP 2019-168781 · Sep 17, 2019 · national
Continuity (2)
Continuation PCTJP2020000352 · Jan 8, 2020
Related Publication 20210384453A1 · Dec 9, 2021
Cited By (2)
US 12,310,163 US 12,532,555