Multi-die peak power management for three-dimensional memory
Embodiments of a peak power management (PPM) circuit on a memory die are disclosed. The PPM circuit includes a first transistor and a second transistor arranged in parallel, wherein the first and second transistors each has a drain terminal electrically connected to a first power source and a second power source, respectively. The PPM circuit also includes a resistor having a first terminal electrically connected to respective source terminals of the first and second transistors. The PPM circuit further includes a first contact pad on the memory die, electrically connected to a second contact pad on a different memory die through a die-to-die connection. The PPM circuit also includes a third transistor with a drain terminal electrically connected to a second terminal of the resistor, and a source terminal electrically connected to the first contact pad.
1. A peak power management circuit on a memory die, comprising:
a first transistor configured to provide a first current from a first power source;
a second transistor configured to provide a second current from a second power source, wherein the first transistor and the second transistor are in parallel and connected at a first terminal;
a first contact pad held at an electrical potential shared with a second contact pad of another peak power management circuit on a different memory die;
a resistor connected in series with the first terminal and the first contact pad; and
a fourth transistor configured to regulate a pull-down current flowing from the first contact pad through the fourth transistor.
2. The peak power management circuit of claim 1 , further comprising:
an amplifier with an input terminal electrically connected to a second terminal of the resistor.
3. The peak power management circuit of claim 2 , wherein the amplifier is a comparator.
4. The peak power management circuit of claim 1 , wherein:
the first and second transistors are p-channel metal oxide semiconductor field effect transistors (MOSFETs).
5. The peak power management circuit of claim 1 , wherein the fourth transistor is an n-channel metal oxide semiconductor field effect transistor (MOSFET).
6. The peak power management circuit of claim 1 , further comprising:
a third transistor, connected in series between the resistor and the first contact pad and configured to regulate a current flowing from the resistor to the first contact pad.
7. The peak power management circuit of claim 6 , wherein the third transistor is an n-channel metal oxide semiconductor field effect transistor (MOSFET).
8. The peak power management circuit of claim 1 , wherein the first contact pad is electrically connected to the second contact pad on the different memory die through wire-bonding.
9. The peak power management circuit of claim 1 , wherein the first contact pad is electrically connected to the second contact pad on the different memory die through flip-chip bonding or die-to-die bonding.
10. The peak power management circuit of claim 1 , wherein the resistor is configured to provide measurement a total current flowing through the resistor, the total current being a sum of the first current and the second current.
11. A method of peak power management (PPM) for two or more memory dies, wherein each of the two or more memory dies comprises a PPM circuit having a contact pad held at an electrical potential shared between the two or more memory dies, the method comprising:
comparing the electrical potential of the contact pad with a first predetermined voltage;
setting a pull-down current to an estimated peak power current when the electrical potential of the contact pad is higher than the first predetermined voltage, wherein the estimated peak power current corresponds to a peak power operation on a selected memory die;
comparing a total current of the PPM circuit on the selected memory die with a maximum current allowed on the selected memory die; and
performing the peak power operation on the selected memory die when the total current is less than the maximum current.
12. The method of claim 11 , wherein the setting the pull-down current comprises regulating the pull-down current through a transistor connected to the contact pad.
13. The method of claim 11 , wherein the comparing the total current with the maximum current comprises measuring a voltage drop across a resistor that is electrically connected to the contact pad.
14. The method of claim 11 , further comprising:
adding a time delay after the setting the pull-down current, wherein the time delay is different between the two or more memory dies.
15. The method of claim 11 , further comprising:
setting the pull-down current to an idle current when the total current is not less than the maximum current.
16. The method of claim 15 , further comprising:
adding a second time delay when a rising edge of the electrical potential of the contact pad is detected or a predetermined maximum time is reached, wherein the second time delay is different for the two or more memory dies.
17. The method of claim 11 , further comprising:
comparing the electrical potential of the contact pad with a second predetermined voltage lower than the first predetermined voltage when the electrical potential of the contact pad is not higher than the first predetermined voltage.
18. The method of claim 17 , further comprising:
setting the pull-down current to the estimated peak power current when the electrical potential of the contact pad is lower than the second predetermined voltage, and when the total current is less than the maximum current subtracting the estimated peak power current.
19. The method of claim 11 , further comprising:
prior to the comparing the total current with the maximum current, comparing the electrical potential of the contact pad with a second predetermined voltage lower than the first predetermined voltage; and
comparing the total current with the maximum current when the electrical potential of the contact pad is less than the second predetermined voltage.
20. The method of claim 11 , further comprising:
providing the total current through a first transistor and a second transistor, comprising:
providing an idle current through the first transistor and a first power source;
providing a second current higher than the idle current through the second transistor and a second power source; and
providing the total current as a sum of the idle current and the second current.
21. A peak power management system on a memory chip with two or more memory dies, comprising:
a peak power management circuit on each of the two or more memory dies, comprising:
a first transistor configured to provide a first current from a first power source;
a second transistor configured to provide a second current from a second power source, wherein the first transistor and the second transistor are in parallel and connected at a first terminal;
a first contact pad held at an electrical potential shared with a second contact pad of another peak power management circuit on a different memory die;
a resistor connected in series with the first terminal and the first contact pad; and
a fourth transistor configured to regulate a pull-down current flowing from the first contact pad through the fourth transistor.
22. The peak power management system of claim 21 , further comprising:
a die-to-die connection configured to electrically connect the first contact pad with the second contact pad.
23. The peak power management system of claim 21 , further comprising:
a comparator with an input terminal electrically connected to a second terminal of the resistor.
24. The peak power management system of claim 21 , further comprising:
a third transistor, connected in series between the resistor and the first contact pad and configured to regulate a current flowing from the resistor to the first contact pad.