Semiconductor memory device and method of manufacturing the same

1. A semiconductor memory device comprising:

a staircase portion provided in a first region of a stacked body and provided with staircases, the stacked body having a plurality of conductive layers and a plurality of insulating layers stacked alternately one by one, the staircase portion having the conductive layers as terrace surfaces, and the staircases being arranged in n rows (where n is an integer of three or more) in a first direction intersecting a stacking direction of the stacked body;

a columnar body provided in a second region of the stacked body, the columnar body penetrating the stacked body in the stacking direction and having a plurality of memory cells at each of positions facing the plurality of conductive layers, and the second region being arranged so as to sandwich the first region in a second direction intersecting the stacking direction and the first direction; and

a plurality of contacts each connected to a respective one of the terrace surfaces,

wherein:

the staircases included in the staircase portion are each formed to ascend for each first step having p (n=p) conductive layers of the plurality of conductive layers in the second direction, and

the terrace surfaces arranged in the first direction, from among the terrace surfaces of the staircases to which the plurality of contacts are connected, are different in height from each other and are formed to ascend for each second step having one conductive layer of the plurality of conductive layers in the first direction.

2. The semiconductor memory device according to claim 1 , further comprising:

a plate-like portion extending in the stacked body in the second direction and dividing the stacked body into a plurality of blocks each including the first region and the second region.

3. The semiconductor memory device according to claim 2 , wherein at least two of the staircase portions are provided in the first region of at least one of the blocks divided by the plate-like portion.

4. The semiconductor memory device according to claim 3 , wherein the terrace surface included in the staircase portion provided in one block includes a conductive layer different from a conductive layer constituting the terrace surface included in another staircase portion.

5. The semiconductor memory device according to claim 4 , wherein:

one staircase portion of the staircase portions provided in one block includes the terrace surface including an uppermost conductive layer of the plurality of conductive layers, and

another staircase portion of the staircase portions provided in one block includes the terrace surface including a lowest conductive layer of the plurality of conductive layers.

6. The semiconductor memory device according to claim 3 , wherein:

the staircase portion provided in one block includes:

a first staircase portion; and

a second staircase portion adjacent to the first staircase portion,

the staircases included in the first staircase portion are formed to ascend toward the second staircase portion for each first step, and

the staircases included in the second staircase portion are formed to ascend toward the first staircase portion for each first step.

7. The semiconductor memory device according to claim 3 , wherein the staircase portions provided in one block are arranged side by side in the second direction.

8. The semiconductor memory device according to claim 2 , wherein the staircase portion arranged in the first direction to sandwich the plate-like portion has a line-symmetric configuration with respect to the plate-like portion in two adjacent blocks of the plurality of blocks.

9. The semiconductor memory device according to claim 8 , wherein the terrace surface arranged in the first direction of the terrace surfaces included individually in the staircase is formed to ascend for each second step toward the plate-like portion in each of the staircase portions provided in the two adjacent blocks.

10. A semiconductor memory device comprising:

a staircase portion provided in a first region of a stacked body and provided with staircases, the stacked body having a plurality of conductive layers and a plurality of insulating layers stacked alternately one by one, the staircase portion having the conductive layers as terrace surfaces, and the staircases being arranged in n rows (where n is an integer of three or more) in a first direction intersecting a stacking direction of the stacked body;

a columnar body provided in a second region of the stacked body, penetrating the stacked body in the stacking direction, and having a plurality of memory cells at each of positions facing the plurality of conductive layers;

a contact connected to one of terrace surfaces; and

a plate-like portion extending in the stacked body in a second direction and dividing the stacked body into a plurality of blocks each including the first region and the second region, the second direction intersecting the stacking direction and the first direction,

wherein:

the staircases included in the staircase portion are each formed to ascend for each first step having p (n=p) conductive layers of the plurality of conductive layers in the second direction,

the terrace surfaces arranged in the first direction are different in height from each other and are formed to ascend for each second step having one conductive layer of the plurality of conductive layers in the first direction, at least two of the staircase portions are provided in one of the blocks divided by the plate-like portion, the staircase portion provided in one block includes: a first staircase portion; and a second staircase portion adjacent to the first staircase portion, the staircases included in the first staircase portion are formed to ascend toward the second staircase portion for each first step, and the staircases included in the second staircase portion are formed to ascend toward the first staircase portion for each first step.