Electrical fuse bit cell in integrated circuit having backside conducting lines

1. An integrated circuit comprising:

a substrate;

a semiconductor structure having active regions therein on the substrate, wherein the semiconductor structure extends in a first direction within an active zone;

a gate-conductor intersecting the semiconductor structure at a channel region of a transistor;

a drain terminal-conductor intersecting the semiconductor structure;

a source terminal-conductor intersecting the semiconductor structure;

a front-side horizontal conducting line extending in the first direction in a first metal layer, wherein the first metal layer is above the gate-conductor and each of the drain terminal-conductor and the source terminal-conductor, and wherein the front-side horizontal conducting line is directly connected to the drain terminal-conductor through a front-side terminal via-connector;

a front-side vertical conducting line extending in a second direction in a second metal layer, the second direction being perpendicular to the first direction, wherein the second metal layer is above the first metal layer, and wherein the front-side vertical conducting line is directly connected to the front-side horizontal conducting line through a front-side metal-to-metal via-connector;

a front-side fuse element having a first fuse terminal conductively connected to the front-side vertical conducting line; and

a backside conducting line directly connected to the source terminal-conductor through a backside terminal via-connector, and wherein the backside conducting line and the front-side fuse element are at opposite sides of the substrate.

2. The integrated circuit of claim 1 , further comprising:

a bit connection line extending in the second direction, wherein the bit connection line is directly connected to a second fuse terminal of the front-side fuse element.

3. The integrated circuit of claim 1 , further comprising:

a word connection line extending in the first direction, wherein the word connection line is directly connected to the gate-conductor through a gate via-connector.

4. The integrated circuit of claim 1 , wherein the backside conducting line is a backside horizontal conducting line extending in the first direction in a first backside metal layer, and wherein the backside horizontal conducting line is directly connected to the source terminal-conductor through the backside terminal via-connector.

5. The integrated circuit of claim 4 , further comprising:

a backside vertical conducting line extending in the second direction in a second backside metal layer, wherein the backside vertical conducting line is directly connected to the backside horizontal conducting line through a backside metal-to-metal via-connector, and wherein the first backside metal layer is between the substrate and the second backside metal layer.

6. The integrated circuit of claim 1 , wherein the backside conducting line is a backside vertical conducting line extending in the first direction in a first backside metal layer, and wherein the backside vertical conducting line is directly connected to the source terminal-conductor through the backside terminal via-connector.

7. The integrated circuit of claim 6 , further comprising:

a backside horizontal conducting line extending in the second direction in a second backside metal layer, wherein the backside vertical conducting line is directly connected to the backside horizontal conducting line through a backside metal-to-metal via-connector, and wherein the first backside metal layer is between the substrate and the second backside metal layer.

8. An integrated circuit comprising:

a substrate;

a semiconductor structure having active regions therein on the substrate, wherein the semiconductor structure is on a front-side of the substrate and extends in a first direction within an active zone;

a gate-conductor intersecting the semiconductor structure at a channel region of a transistor;

a source terminal-conductor intersecting the semiconductor structure at a source region of the transistor;

a drain terminal-conductor intersecting the semiconductor structure at a drain region of the transistor;

a first front-side horizontal conducting line extending in the first direction in a first metal layer, wherein the first metal layer is above the gate-conductor and each of the source terminal-conductor and the drain terminal-conductor, and wherein the first front-side horizontal conducting line is directly connected to the source terminal-conductor through a front-side terminal via-connector;

a backside conducting line directly connected to the drain terminal-conductor through a backside terminal via-connector, and wherein the backside conducting line is on a backside of the substrate; and

a backside fuse element conductively connected to the backside conducting line, and wherein the backside fuse element and the first front-side horizontal conducting line are at opposite sides of the substrate.

9. The integrated circuit of claim 8 , wherein the backside conducting line is a backside horizontal conducting line extending in the first direction in a first backside metal layer.

10. The integrated circuit of claim 9 , further comprising:

a backside vertical conducting line extending in a second direction in a second backside metal layer, the second direction being perpendicular to the first direction;

wherein the backside vertical conducting line is directly connected to the backside horizontal conducting line through a backside metal-to-metal via-connector; and

wherein the backside fuse element is conductively connected to the backside vertical conducting line through a via connector.

11. The integrated circuit of claim 9 , wherein the backside fuse element is in a third backside metal layer.

12. The integrated circuit of claim 8 , wherein the backside conducting line is a backside vertical conducting line extending in a second direction in a first backside metal layer, the second direction being perpendicular to the first direction.

13. The integrated circuit of claim 12 , further comprising:

a backside horizontal conducting line extending in the first direction in a second backside metal layer;

wherein the backside vertical conducting line is directly connected to the backside horizontal conducting line through a backside metal-to-metal via-connector; and

wherein the backside fuse element is conductively connected to the backside horizontal conducting line through a via connector.

14. The integrated circuit of claim 12 , wherein the backside fuse element is in the first backside metal layer.

15. The integrated circuit of claim 8 , further comprising:

a second front-side horizontal conducting line extending in the first direction in the first metal layer, wherein the second front-side horizontal conducting line is directly connected to the drain terminal-conductor through a second front-side terminal via-connector; and

a front-side fuse element conductively connected to the second front-side horizontal conducting line.

16. The integrated circuit of claim 15 , further comprising:

a second front-side vertical conducting line extending in a second direction in a second metal layer, the second direction being perpendicular to the first direction wherein the second front-side vertical conducting line is directly connected to the second front-side horizontal conducting line through a front-side metal-to-metal via-connector; and

wherein the front-side fuse element is conductively connected to the second front-side vertical conducting line.

17. A method comprising:

fabricating a plurality of transistors on a front-side of a substrate, wherein the transistor includes a gate-conductor, a source terminal-conductor, and a drain terminal-conductor;

depositing insulating materials over the gate-conductor and each of the source terminal-conductor and the drain terminal-conductor;

depositing a first metal layer over the insulating materials and patterning the first metal layer to form front-side horizontal conducting lines extending in a first direction, and wherein the front-side horizontal conducting lines include a front-side horizontal conducting line directly connected to the source terminal-conductor through a front-side terminal via-connector;

depositing a second metal layer over a layer of inter-layer dielectric that overlies the first metal layer and patterning the second metal layer to form front-side vertical conducting lines extending in a second direction that is perpendicular to the first direction, and wherein a front-side vertical conducting line is directly connected to the front-side horizontal conducting line through a front-side metal-to-metal via-connector;

depositing a first backside metal layer at a backside of the substrate and patterning the first backside metal layer to form backside first-metal conducting lines which includes a backside first-metal conducting line directly connected to the drain terminal-conductor through a backside terminal via-connector;

depositing a second backside metal layer over a first layer of backside inter-layer dielectric overlying the first backside metal layer and patterning the second backside metal layer to form backside second-metal conducting lines which includes a backside second-metal conducting line directly connected to the backside first-metal conducting line through a metal-to-metal via-connector; and

forming a backside fuse element either in the second backside metal layer or in a third backside metal layer, wherein the third backside metal layer is over a second layer of backside inter-layer dielectric overlying the second backside metal layer, wherein the backside fuse element is conductively connected to the backside second-metal conducting line.

18. The method of claim 17 , wherein the backside first-metal conducting line is a backside horizontal conducting line extending in the first direction and the backside second-metal conducting line is a backside vertical conducting line extending in the second direction, wherein forming the backside fuse element comprises:

forming the backside fuse element in the third backside metal layer.

19. The method of claim 17 , wherein the backside first-metal conducting line is a backside vertical conducting line extending in the second direction and the backside second-metal conducting line is a backside horizontal conducting line extending in the first direction, wherein forming the backside fuse element comprises:

forming the backside fuse element in the second backside metal layer.

20. The method of claim 17 , further comprising:

depositing a third backside metal layer over a second layer of backside inter-layer dielectric overlying the second backside metal layer; and

forming a front-side fuse element in the third backside metal layer conductively connected to a second front-side vertical conducting line;

wherein the patterning the first metal layer comprises patterning the first metal layer to form the front-side horizontal conducting lines which includes a second front-side horizontal conducting line directly connected to the drain terminal-conductor through a second front-side terminal via-connector,

wherein the patterning the second metal layer comprises patterning the second metal layer to form the front-side vertical conducting lines which includes the second front-side vertical conducting line directly connected to the second front-side horizontal conducting line through a second front-side metal-to-metal via-connector.