IP Library › Granted Patent US 12,189,988
Granted Patent B2
US 12,189,988 · App. 17/414,298 · Granted Jan 7, 2025

Write broadcast operations associated with a memory device

Inventors: Dmitri A. Yudanov (Rancho Cordova, CA); Shanky Kumar Jain (Folsom, CA)
Assignee: Micron Technology, Inc.
G06F3/0659G06F3/0604G06F3/0673G06F9/546G06F12/0246G06F12/0802G06F12/0873G06F12/0875G06F12/0893G06F12/1045G11C7/08G11C7/1012G11C7/1063G11C7/109G11C8/08G11C11/221G11C11/2257G11C11/2259G11C11/2273G11C11/2275G11C11/2297G11C11/406G11C11/40603G11C11/4074G11C11/4085G11C11/4091G11C11/4096G06F2212/60G06F2212/608G06F2212/72G06F2212/7201
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Quick Facts
Patent No.
US 12,189,988
App. No.
17/414,298
Granted
Jan 7, 2025
Kind
B2
Abstract

Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable write broadcast operations. A write broadcast may occur from one or more signal development components or from one or more multiplexers to multiple locations of the memory array.

Claims (104)

1. A method, comprising:

determining a pattern of logic states for storing in a memory device;

storing, at a first component of the memory device, a plurality of signal states associated with the pattern of logic states;

determining, at a second component of the memory device, a plurality of locations for storing the pattern of logic states, wherein each location of the plurality of locations is associated with a respective word line of a plurality of word lines;

transferring, via the first component, data associated with the pattern of logic states from at least one location of the plurality of locations to a sense component array based at least in part on the determining of the plurality of locations; and

writing the pattern of logic states to the plurality of locations of the second component based at least in part on the plurality of signal states stored at the first component and concurrently activating multiple word lines of the plurality of word lines.

2. The method of claim 1 , wherein the pattern of logic states comprise one or more logic states, and writing the pattern of logic states to the plurality of locations of the second component comprises:

writing the one or more logic states to each location of the plurality of locations of the second component based at least in part on the pattern of logic states.

3. The method of claim 1 , wherein the first component of the memory device comprises a capacitor array, a signal development cache component, a multiplexer, or any combination thereof.

4. The method of claim 1 , wherein the second component of the memory device comprises a memory array different from the first component of the memory device.

5. The method of claim 1 , wherein:

the second component comprises a plurality of domains or subdomains;

each domain or subdomain of the plurality of domains or subdomains comprises at least one location of the plurality of locations and a plurality of access lines coupled with the at least one location; and

the pattern of logic states is written to the at least one location using the plurality of access lines.

6. The method of claim 1 , further comprising:

receiving, at the memory device from a requesting device, a command associated with the pattern of logic states, wherein determining the pattern of logic states is based at least in part on receiving the command.

7. The method of claim 6 , further comprising:

modifying the pattern of logic states based at least in part on the command, wherein the pattern of logic states is modified using the first component or using a sense component array.

8. The method of claim 6 , wherein the command comprises a write command, a read command, a modify command, or any combination thereof.

9. A method comprising:

determining a pattern of logic states for storing in a memory device;

storing, at a first component of the memory device, a plurality of signal states associated with the pattern of logic states;

determining, at a second component of the memory device, a plurality of locations for storing the pattern of logic states, wherein each location of the plurality of locations is associated with a respective word line of a plurality of word lines;

activating a first set of multiple word lines of the plurality of word lines concurrently;

applying a first signal to a set of multiple signal lines coupled with the plurality of locations after activating the first set of multiple word lines, wherein the first signal corresponds to a first logic state;

activating a second set of multiple word lines of the plurality of word lines concurrently based at least in part on applying the first signal;

applying a second signal to the set of multiple signal lines after activating the second set of multiple word lines, wherein the second signal corresponds to a second logic state; and

writing the pattern of logic states to the plurality of locations of the second component based at least in part on the plurality of signal states stored at the first component and concurrently activating multiple word lines of the plurality of word lines.

10. The method of claim 9 , further comprising:

writing the pattern of logic states to the plurality of locations of the second component based at least in part on applying the first signal and the second signal to the set of multiple signal lines.

11. A method comprising:

determining a pattern of logic states for storing in a memory device;

storing, at a first component of the memory device, a plurality of signal states associated with the pattern of logic states;

coupling the first component with a sense component array;

capturing the plurality of signal states at the sense component array based at least in part on the coupling;

coupling a plurality of signal lines with the sense component array via a plurality of selection components;

determining a plurality of locations of a second component of the memory device for storing the pattern of logic states, wherein each location of the plurality of locations is associated with a respective word line of a plurality of word lines; and

writing the pattern of logic states to the plurality of locations of the second component based at least in part on concurrently activating multiple word lines of the plurality of word lines and coupling the plurality of signal lines with the sense component array.

12. A method comprising:

determining a pattern of logic states for storing in a memory device;

storing, at a first component of the memory device, a plurality of signal states associated with the pattern of logic states;

coupling the first component with a sense component array;

transferring, via the sense component array, the plurality of signal states to the first component;

decoupling the first component from the sense component array;

coupling a plurality of signal lines with the first component;

determining, at a second component of the memory device, a plurality of locations for storing the pattern of logic states, wherein each location of the plurality of locations is associated with a respective word line of a plurality of word lines; and

writing the pattern of logic states to the plurality of locations of the second component based at least in part on the plurality of signal states stored at the first component, concurrently activating multiple word lines of the plurality of word lines, and coupling the plurality of signal lines with the first component.

13. A memory device, comprising:

a first component operable to store a plurality of signal states associated with a pattern of logic states;

a second component comprising a plurality of locations, wherein each location of the plurality of locations is associated with a respective word line of a plurality of word lines; and

a plurality of access lines, comprising the plurality of word lines, the plurality of access lines comprising a set of signal lines coupled with the plurality of locations, a first set of the plurality of word lines associated with the plurality of locations of the second component, and at least a second set of the plurality of word lines associated with the plurality of locations of the second component,

wherein the first set of the plurality of word lines and the second set of the plurality of word lines are operable to write a respective copy of the pattern of logic states to each location of the plurality of locations of the second component based at least in part on the plurality of signal states stored at the first component and concurrently activating multiple word lines of the plurality of word lines, and operable to write the plurality of signal states to the first component based at least in part on the pattern of logic states stored at the plurality of locations of the second component.

14. The memory device of claim 13 , further comprising:

a signal source operable to:

apply a first signal corresponding to a first logic state to the set of signal lines after activating multiple word lines of the first set of the plurality of word lines concurrently; and

apply at least a second signal corresponding to a second logic state to the set of signal lines after activating multiple word lines of the second set of the plurality of word lines concurrently.

15. The memory device of claim 13 , wherein the second component further comprises a plurality of domains or subdomains, wherein each domain or subdomain of the plurality of domains or subdomains comprises at least one location of the plurality of locations for storing the pattern of logic states.

16. A memory device, comprising:

a first component operable to store a plurality of signal states associated with a pattern of logic states;

a second component comprising a plurality of locations, wherein each location of the plurality of locations is associated with a respective word line of a plurality of word lines;

and

a plurality of access lines, comprising the plurality of word lines, operable to write a respective copy of the pattern of logic states to each location of the plurality of locations of the second component based at least in part on the plurality of signal states stored at the first component and concurrently activating multiple word lines of the plurality of word lines, and operable to write the plurality of signal states to the first component based at least in part on the pattern of logic states stored at the plurality of locations of the second component, wherein:

the pattern of logic states comprise one or more logic states;

the plurality of access lines are further operable to write the one or more logic states to each location of the plurality of locations of the second component based at least in part on the pattern of logic states; and

the plurality of access lines are further operable to store one or more signal states at the first component based at least in part on the pattern of logic states.

17. A memory device comprising:

a first component operable to store a plurality of signal states associated with a pattern of logic states;

a second component comprising a plurality of locations, wherein each location of the plurality of locations is associated with a respective word line of a plurality of word lines;

a sense component array couplable with the first component, wherein the first component is further operable to capture the plurality of signal states at the sense component array based at least in part on coupling the sense component array with the first component; and

a plurality of access lines, comprising the plurality of word lines, operable to write a respective copy of the pattern of logic states to each location of the plurality of locations of the second component based at least in part on the plurality of signal states stored at the first component and concurrently activating multiple word lines of the plurality of word lines, and operable to write the plurality of signal states to the first component based at least in part on the pattern of logic states stored at the plurality of locations of the second component.

18. The memory device of claim 17 , wherein:

the sense component array is selectively couplable with the plurality of access lines via a plurality of selection components; and

writing the pattern of logic states to the plurality of locations of the second component is further based at least in part on coupling the plurality of access lines with the sense component array.

19. A memory device, comprising:

a first component;

a second component; and

one or more controllers operable to cause the memory device to:

determine a pattern of logic states for storing at the memory device;

store, at the first component, a plurality of signal states associated with the pattern of logic states;

determine a plurality of locations of the second component for storing the pattern of logic states, wherein each location of the plurality of locations is associated with a respective word line of a plurality of word lines;

transfer, via the first component, data associated with the pattern of logic states from at least one location of the plurality of locations to a sense component array based at least in part on the determining of the plurality of locations; and

write the pattern of logic states to the plurality of locations of the second component based at least in part on the plurality of signal states stored at the first component and concurrently activating multiple word lines of the plurality of word lines.

20. The memory device of claim 19 , wherein the one or more controllers are further operable to cause the memory device to:

activate a first set of multiple word lines of the plurality of word lines concurrently;

apply a first signal to a set of multiple signal lines coupled with the plurality of locations after activating the first set of multiple word lines, wherein the first signal corresponds to a first logic state;

activate a second set of multiple word lines of the plurality of word lines concurrently based at least in part on applying the first signal; and

apply a second signal to the set of multiple signal lines after activating the second set of multiple word lines, wherein the second signal corresponds to a second logic state, and wherein writing the pattern of logic states to the plurality of locations of the second component is based at least in part on applying the first signal and the second signal to the set of multiple signal lines.

21. The memory device of claim 19 , wherein the pattern of logic states comprise one or more logic states, the one or more controllers further operable to cause the memory device to:

write the one or more logic states to each location of the plurality of locations of the second component based at least in part on the pattern of logic states.

22. The memory device of claim 19 , wherein the one or more controllers are further operable to cause the memory device to:

receive, from a requesting device, a command associated with the pattern of logic states, wherein determining the pattern of logic states is based at least in part on receiving the command.

23. The memory device of claim 22 , wherein the one or more controllers are further operable to cause the memory device to:

modify the pattern of logic states based at least in part on the command, wherein the pattern of logic states is modified using the first component or using a sense component array.

24. A memory device, comprising:

a first component;

a second component; and

one or more controllers operable to cause the memory device to:

determine a pattern of logic states for storing at the memory device;

store, at the first component, a plurality of signal states associated with the pattern of logic states;

couple the first component with a sense component array;

capture the plurality of signal states at the sense component array based at least in part on coupling the first component with the sense component array;

couple a plurality of signal lines with the sense component array via a plurality of selection components;

determine a plurality of locations of the second component for storing the pattern of logic states, wherein each location of the plurality of locations is associated with a respective word line of a plurality of word lines; and

write the pattern of logic states to the plurality of locations of the second component based at least in part on concurrently activating multiple word lines of the plurality of word lines and coupling the plurality of signal lines with the sense component array.

Continuity (2)
Provisional Application 62783388 · Dec 21, 2018
Related Publication 20220020424A1 · Jan 20, 2022
References Cited (197)
US 4493026A · Olnowich · 1985 [cited by applicant]
US 5226009A · Arimoto · 1993 [cited by applicant]
US 5341501A · Keeley et al. · 1994 [cited by applicant]
US 5377154A · Takasugi · 1994 [cited by applicant]
US 5596521A · Tanaka et al. · 1997 [cited by applicant]
US 5787267A · Leung et al. · 1998 [cited by applicant]
US 5818787A · Miyamoto et al. · 1998 [cited by applicant]
US 5875452A · Katayama et al. · 1999 [cited by applicant]
US 5909407A · Yamamoto et al. · 1999 [cited by applicant]
US 6205076B1 · Wakayama et al. · 2001 [cited by applicant]
US 6320778B1 · Tanaka et al. · 2001 [cited by applicant]
US 7085190B2 · Worley et al. · 2006 [cited by applicant]
US 7216272B2 · Loh · 2007 [cited by applicant]
US 7286425B2 · Barth · 2007 [cited by applicant]
US 8090999B2 · Roohparvar · 2012 [cited by applicant]
US 8873329B1 · Zheng et al. · 2014 [cited by applicant]
US 9313435B2 · Nitta et al. · 2016 [cited by applicant]
US 9443602B2 · Sakaue et al. · 2016 [cited by applicant]
US 9509317B2 · Masleid · 2016 [cited by examiner]
US 9535844B1 · Cooney et al. · 2017 [cited by applicant]
US 9761312B1 · Kajigaya · 2017 [cited by applicant]
US 10153020B1 · Vimercati · 2018 [cited by applicant]
US 10395710B1 · Abedifard et al. · 2019 [cited by applicant]
US 20010026465A1 · Choi et al. · 2001 [cited by applicant]
US 20010050873A1 · Tanaka et al. · 2001 [cited by applicant]
US 20020067650A1 · Tanaka et al. · 2002 [cited by applicant]
US 20020154536A1 · Perner · 2002 [cited by applicant]
US 20020161967A1 · Kirihata et al. · 2002 [cited by applicant]
US 20020181307A1 · Fifield et al. · 2002 [cited by applicant]
US 20020186591A1 · Lee et al. · 2002 [cited by applicant]
US 20030107923A1 · Roohparvar · 2003 [cited by applicant]
US 20040240288A1 · Takahashi · 2004 [cited by applicant]
US 20050030817A1 · Luk et al. · 2005 [cited by applicant]
US 20060056264A1 · Worley et al. · 2006 [cited by applicant]
US 20060087894A1 · Kim · 2006 [cited by applicant]
US 20060214086A1 · Fukushima · 2006 [cited by applicant]
US 20060221704A1 · Li et al. · 2006 [cited by applicant]
US 20070061507A1 · Iwanari et al. · 2007 [cited by applicant]
US 20070097768A1 · Barth · 2007 [cited by applicant]
US 20070168836A1 · Dempsey et al. · 2007 [cited by applicant]
US 20070250667A1 · Dement et al. · 2007 [cited by applicant]
US 20080037356A1 · Kajigaya · 2008 [cited by applicant]
US 20080080266A1 · Khellah et al. · 2008 [cited by applicant]
US 20080239811A1 · Tanaka · 2008 [cited by applicant]
US 20090268537A1 · Kajigaya · 2009 [cited by applicant]
US 20100128515A1 · Fukushi · 2010 [cited by applicant]
US 20110044095A1 · Sato et al. · 2011 [cited by applicant]
US 20110119451A1 · Fuller et al. · 2011 [cited by applicant]
US 20110205776A1 · Murata · 2011 [cited by applicant]
US 20110208901A1 · Kim et al. · 2011 [cited by applicant]
US 20110246729A1 · Smith · 2011 [cited by applicant]
US 20110280086A1 · Choi et al. · 2011 [cited by applicant]
US 20120082174A1 · Chen et al. · 2012 [cited by applicant]
US 20120127805A1 · Dreesen et al. · 2012 [cited by applicant]
US 20120151232A1 · Fish, III · 2012 [cited by applicant]
US 20120159076A1 · Tanpure et al. · 2012 [cited by applicant]
US 20120243304A1 · Hoya · 2012 [cited by applicant]
US 20120300566A1 · Mueller et al. · 2012 [cited by applicant]
US 20130145097A1 · Ingle et al. · 2013 [cited by applicant]
US 20130242684A1 · Takizawa · 2013 [cited by applicant]
US 20140177343A1 · Chan et al. · 2014 [cited by applicant]
US 20140181424A1 · Park · 2014 [cited by applicant]
US 20140325129A1 · Ahlquist · 2014 [cited by applicant]
US 20150130971A1 · Oike et al. · 2015 [cited by applicant]
US 20150229859A1 · Guidash et al. · 2015 [cited by applicant]
US 20160155481A1 · Park · 2016 [cited by applicant]
US 20160179685A1 · Byun · 2016 [cited by applicant]
US 20160239060A1 · Koob et al. · 2016 [cited by applicant]
US 20160283392A1 · Greenfield et al. · 2016 [cited by applicant]
US 20160336055A1 · Kato · 2016 [cited by applicant]
US 20160350230A1 · Murphy · 2016 [cited by applicant]
US 20170133096A1 · Yoo et al. · 2017 [cited by applicant]
US 20170153826A1 · Cho et al. · 2017 [cited by applicant]
US 20170263304A1 · Vimercati · 2017 [cited by applicant]
US 20170270051A1 · Chen et al. · 2017 [cited by applicant]
US 20170271019A1 · Park et al. · 2017 [cited by applicant]
US 20170277637A1 · Willcock et al. · 2017 [cited by applicant]
US 20170315737A1 · Kajigaya · 2017 [cited by applicant]
US 20170337149A1 · Onuki et al. · 2017 [cited by applicant]
US 20170365358A1 · Ha · 2017 [cited by applicant]
US 20180081774A1 · Kawamura et al. · 2018 [cited by applicant]
US 20180130506A1 · Kang et al. · 2018 [cited by applicant]
US 20180150398A1 · Lu · 2018 [cited by applicant]
US 20180181344A1 · Tomishima et al. · 2018 [cited by applicant]
US 20180247687A1 · Vimercati · 2018 [cited by applicant]
US 20180301180A1 · Sano · 2018 [cited by applicant]
US 20180308538A1 · Vo et al. · 2018 [cited by applicant]
US 20180314635A1 · Alam · 2018 [cited by applicant]
US 20180349292A1 · Tal et al. · 2018 [cited by applicant]
US 20180358078A1 · Vimercati · 2018 [cited by applicant]
US 20190103145A1 · Tseng et al. · 2019 [cited by applicant]
US 20200073812A1 · Willcock et al. · 2020 [cited by applicant]
US 20200135261A1 · Haraguchi · 2020 [cited by examiner]
US 20210142845A1 · Murphy · 2021 [cited by applicant]
CN 1212430A · 1999 [cited by applicant]
CN 1480950A · 2004 [cited by applicant]
CN 1698132A · 2005 [cited by applicant]
CN 101063957A · 2007 [cited by applicant]
CN 101171641A · 2008 [cited by applicant]
CN 101379566A · 2009 [cited by applicant]
CN 101558390A · 2009 [cited by applicant]
CN 101743597A · 2010 [cited by applicant]
CN 102656639A · 2012 [cited by applicant]
CN 102800349A · 2012 [cited by applicant]
CN 103221929A · 2013 [cited by applicant]
CN 104078077A · 2014 [cited by applicant]
CN 105739914A · 2016 [cited by applicant]
CN 106463172A · 2017 [cited by applicant]
CN 106683692A · 2017 [cited by applicant]
CN 107240410A · 2017 [cited by applicant]
CN 107408405A · 2017 [cited by applicant]
CN 107430550A · 2017 [cited by applicant]
CN 107683505A · 2018 [cited by applicant]
CN 107924364A · 2018 [cited by applicant]
CN 108121671A · 2018 [cited by applicant]
CN 108701077A · 2018 [cited by applicant]
CN 108780656A · 2018 [cited by applicant]
CN 108885595A · 2018 [cited by applicant]
CN 108885891A · 2018 [cited by applicant]
EP 0662663A2 · 1995 [cited by applicant]
EP 0717412B1 · 2002 [cited by applicant]
JP 63197099A · 1988 [cited by applicant]
JP 01166850A · 1989 [cited by applicant]
JP 03015958A · 1991 [cited by applicant]
JP 05217374A · 1993 [cited by applicant]
JP 07211057A · 1995 [cited by applicant]
JP 07211061A · 1995 [cited by applicant]
JP 09180437A · 1997 [cited by applicant]
JP 11066850A · 1999 [cited by applicant]
JP 11073763A · 1999 [cited by applicant]
JP 11339466A · 1999 [cited by applicant]
JP 2000020396A · 2000 [cited by applicant]
JP 2001005725A · 2001 [cited by applicant]
JP 2001006379A · 2001 [cited by applicant]
JP 2001273193A · 2001 [cited by applicant]
JP 2002334580A · 2002 [cited by applicant]
JP 2003007049A · 2003 [cited by applicant]
JP 2004348916A · 2004 [cited by applicant]
JP 2006236304A · 2006 [cited by applicant]
JP 2007048286A · 2007 [cited by applicant]
JP 2007080325A · 2007 [cited by applicant]
JP 2012198972A · 2012 [cited by applicant]
JP 2012203938A · 2012 [cited by applicant]
JP 2013196717A · 2013 [cited by applicant]
JP 2017212022A · 2017 [cited by applicant]
JP 2018503903A · 2018 [cited by applicant]
JP 2018181394A · 2018 [cited by applicant]
KR 20070066185A · 2007 [cited by applicant]
KR 20100113389 · 2010 [cited by applicant]
KR 20100113389A · 2010 [cited by applicant]
TW 200426833A · 2004 [cited by applicant]
TW 201735038A · 2017 [cited by applicant]
TW 201805945A · 2018 [cited by applicant]
TW 201824280A · 2018 [cited by applicant]
TW I630621B · 2018 [cited by applicant]
WO 2017136203A1 · 2017 [cited by applicant]
WO 2017192759A1 · 2017 [cited by applicant]
WO 2018125385A1 · 2018 [cited by applicant]
WO 2018163252A1 · 2018 [cited by applicant]
Japan Patent Office, “Decision to Grant a Patent”, issued in connection with Japan Patent Application No. 2021-535529 dated Jun. 14, 2022 (5 pages). [cited by applicant]
Japan Patent Office, “Notice of Rejection Ground”, issued in connection with Japan Patent Application No. 2021-535534 dated Jul. 5, 2022 (19 pages). [cited by applicant]
Japan Patent Office, “Notice of Rejection Ground”, issued in connection with Japan Patent Application No. 2021-535536 dated Jul. 5, 2022 (18 pages). [cited by applicant]
Japan Patent Office, “Office Action”, issued in connection with Japan Patent Application No. 2021-535540 dated Jun. 21, 2022 (17 pages). [cited by applicant]
Japan Patent Office, “Notice of Rejection Ground,” issued in connection with Japanese Patent Application No. 2021-535559, dated Feb. 1, 2022 (10 pages). [cited by applicant]
ISA/KR, International Search Report and Written Opinion of the International Searching Authority, Int'l Appl. No. PCT/US2019/067829, Apr. 28, 2020, Korean Intellectual Property Office, Seo-gu, Daejeon, Republic of Korea… [cited by applicant]
ISA/KR, International Search Report and Written Opinion of the International Searching Authority, Int'l Appl. No. PCT/US2019/067840, Apr. 28, 2020, Korean Intellectual Property Office, Seo-gu, Daejeon, Republic of Korea… [cited by applicant]
ISA/KR, International Search Report and Written Opinion of the International Searching Authority, Int'l Appl. No. PCT/US2019/067844, Apr. 28, 2020, Korean Intellectual Property Office, Seo-gu, Daejeon, Republic of Korea… [cited by applicant]
ISA/KR, International Search Report and Written Opinion of the International Searching Authority, Int'l Appl. No. PCT/US2019/067834, Apr. 28, 2020, Korean Intellectual Property Office, Seo-gu, Daejeon, Republic of Korea… [cited by applicant]
ISA/KR, International Search Report and Written Opinion of the International Searching Authority, Int'l Appl. No. PCT/US2019/067832, Apr. 28, 2020, Korean Intellectual Property Office, Seo-gu, Daejeon, Republic of Korea… [cited by applicant]
ISA/KR, International Search REport and Written Opinion of the International Searching Authority, Int'l Appl. No. PCT/US2019/067838, Apr. 28, 2020, Korean Intellectual Property Office, Seo-gu, Daejeon, Republic of Korea… [cited by applicant]
ISA/KR, International Search Report and Written Opinion of the International Searching Authority, Int'l. Appl. No. PCT/US2019/064597, Mar. 20, 2020, Korean Intellectual Property Office, Seo-gu, Daejeon, Republic of Kore… [cited by applicant]
Intellectual Property Office, “Office Action,” issued in connection with ROC (Taiwan) Patent Application No. 108144214, dated Oct. 26, 2020 (6 pages). [cited by applicant]
Taiwan Intellectual Property Office, “Office Action,” issued in connection with ROC (Taiwan) Patent Application No. 108144214, dated Sep. 28, 2021 (18 pages with translation). [cited by applicant]
European Patent Office, “Supplementary European search report and Search Opinion”, issued in connection with European Patent Application No. 19900061.3 dated Aug. 30, 2022 (9 pages). [cited by applicant]
Japan Patent Office, “Notice of Rejection Ground”, issued in connection with Japan Patent Application No. 2021-533432 dated Aug. 16, 2022 (29 pages). [cited by applicant]
China National Intellectual Property Administration, “First Office Action,” issued in connection with Chinese Application No. 201980084160.X, dated Jan. 11, 2022 (13 pages). [cited by applicant]
Aboughazaleh, N. et al., “Near-memory Caching for Improved Energy Consumption”, Proceedings of the 2005 International Conference on Computer Design (ICCD'05), Oct. 2, 2005, pp. 105-110. [cited by applicant]
European Patent Office, “Supplementary European search report and Search Opinion”, issued in connection with European Patent Application No. 19898746.3 dated Sep. 9, 2022 (9 pages). [cited by applicant]
European Patent Office, “Supplementary European search report and Search Opinion”, issued in connection with European Patent Application No. 19899500.3 dated Sep. 12, 2022 (9 pages). [cited by applicant]
European Patent Office, “Supplementary European search report and Search Opinion”, issued in connection with European Patent Application No. 19900287.4 dated Sep. 14, 2022 (11 pages). [cited by applicant]
European Patent Office, “Supplementary European search report and Search Opinion”, issued in connection with European Patent Application No. 19900288.2 dated Sep. 15, 2022 (10 pages). [cited by applicant]
European Patent Office, “Supplementary European search report and Search Opinion”, issued in connection with European Patent Application No. 19900916.8 dated Sep. 16, 2022 (10 pages). [cited by applicant]
Japan Patent Office, “Notice of Rejection Ground”, issued in connection with Japan Patent Application No. 2021-533238 dated Sep. 6, 2022 (16 pages). [cited by applicant]
Chinese Patent Office, “Office Action,” issued in connection with Chinese Patent Application No. 201980082612.0 dated Oct. 9, 2023 (16 pages total; 8 pages Original & 8 pages machine translation). [cited by applicant]
Chinese Patent Office, “Office Action,” issued in connection with Chinese Patent Application No. 201980084236.9 dated Sep. 4, 2023 (16 pages total; 8 pages Original & 8 pages machine translation). [cited by applicant]
Chinese Patent Office, “Office Action,” issued in connection with Chinese Patent Application No. 201980084464.6 dated Aug. 1, 2023 (32 pages) (12 pages of English Translation and 20 pages of Original Document). [cited by applicant]
Japan Patent Office, “Office Action,” issued in connection with Japan Patent Application No. 2022-168730 dated Sep. 5, 2023 (13 pages) (7 pages of English Translation and 6 pages of Original Document). [cited by applicant]
John Kirkwood, “Sybase SQL Server 11”, Hope, Oct. 31, 1998, pp. 169-270. [cited by applicant]
Xin, X., “Design and Application: CAM Based on FPGA”, Journal Of National University Of Defense Technology, vol. 23, No. 5, 2001, 5 pages. (English Abstract attached). [cited by applicant]
Zhou Ke, Research on Storage Optimization Based on Solid State Drive's Characteristics, Huazhong University of Science & Technology, Feb. 2013, 116 pages. (English Abstract attached). [cited by applicant]
Cao, Z., et al., “Fast bipolar 1024-bit random access memory (RAM) for high performance storage system”, Computer research and development, Issue 01, Jan. 15, 1978, 7 pages. [cited by applicant]
Chinese Patent Office, “Office Action,” issued in connection with Chinese Patent Application No. 201980082657.8 dated Nov. 1, 2023 (16 pages total; 10 pages Original & 6 pages machine translation). [cited by applicant]
Chinese patent office, “China Office Action,” issued in connection with China Patent Application No. 201980084464.6 dated Feb. 23, 2024 (33 pages) (13 pages of English Translation and 20 pages of Original Document). [cited by applicant]
Chinese patent office, “CN Notice of Allowance,” issued in connection with China Patent Application No. 201980084236.9 dated Feb. 4, 2024 (8 pages total; 4 pages Original & 4 pages translation). [cited by applicant]
Chinese patent office, “CN Notice of Allowance, including Search Report,” issued in connection with China Patent Application No. 201980084464.6 dated Jul. 11, 2024 (4 pages). [cited by applicant]
Chinese patent office, “China Office Action,” issued in connection with China Patent Application No. 201980084212.3 dated Oct. 31, 2024 (10 pages). [cited by applicant]
Chinese patent office, “China Office Action,” issued in connection with China Patent Application No. 201980084577.6 dated Oct. 31, 2024 (7 pages). [cited by applicant]