Instruction driven dynamic clock management for deep pipeline and out-of-order operation of microprocessor using on-chip critical path messenger and elastic pipeline clocking
Systems and/or methods can include techniques to exploit dynamic timing slack on the chip. By using a special clock generator, the clock period can be shrunk as needed at every cycle. The clock period is determined during operation by checking “critical path messengers” to indicate how much dynamic timing slack exists. Elastic pipeline timing can also be introduced to redistribute timing among pipeline stages to bring further benefits.
1. A dynamic clock management method for executing instructions in deep pipeline stages of a processor, comprising:
determining a dynamic timing slack (DTS) of all pipeline stages in each local clock cycle, wherein the DTS is a time margin between an actual timing period and a worst-case clock period to process all in-flight instructions by all the pipeline stages of a computing unit (CU) at a current local clock cycle, wherein the pipeline stages in the CU comprise: a first sequence of control pipeline stages followed by a second sequence of task execution pipeline stages;
adjusting by increasing or decreasing a local clock period at the current local clock cycle, by a predetermined amount of time according to a determined DTS, for all the pipeline stages;
executing in real-time at the current clock cycle, the in-flight instructions in each of the pipeline stages according to an adjusted local clock period; and
repeat execution of subsequent in-flight instructions in each of the pipeline stages according to a subsequent adjusted local clock period, wherein the subsequent adjusted local clock period is dynamically adjusted according to a subsequent determined DTS at a subsequent clock cycle.
2. The dynamic clock management method of claim 1 , wherein the DTS determination comprising receiving simultaneously respective critical path messenger signal sent one local clock cycle earlier, from each of the first sequence of control pipeline stages and the second sequence of execution pipeline stages.
3. The dynamic clock management method of claim 2 , wherein the respective critical path messenger signal sent from each of the first sequence of control pipeline stages is triggered by a detection of a data transitioning and a presence of a critical path corresponding to a particular pipeline stage in the first sequence of control pipeline stages sent one local clock cycle earlier.
4. The dynamic clock management method of claim 2 , wherein the respective critical path messenger signal sent from each of the second sequence of task execution pipeline stages is triggered by receiving of a real-time issued instruction Opcode or function code corresponding to a particular pipeline stage in a second sequence of task execution pipeline stages sent one local clock cycle earlier.
5. The dynamic clock management method of claim 1 , wherein the adjusting of the local clock period comprising adjusting a phase of an on-chip delay locked loop (DLL) local clock generator to cause a rising edge of the local clock period to shift forward or backward by a time duration according to the determined DTS at the current local clock cycle.
6. The dynamic clock management method of claim 5 , wherein the adjusting of the phase of the on-chip DLL local clock generator comprising communicating to an on-chip timing arbiter circuit to select a suitable amount of phase adjustment to the on-chip DLL local clock generator.
7. The dynamic clock management method of claim 6 , wherein the on-chip timing arbiter circuit performs an elastic timing redistribution locally and individually, by adding an additional phase adjustment to provide additional timing margin to the local clock period in order to mitigate a timing bottleneck to one or more selected first sequence of control pipeline stages.
8. The dynamic clock management method of claim 7 , wherein the an elastic timing redistribution further comprising the on-chip timing arbiter circuit fixing the local clock period of one or more of the second sequence execution pipeline stages at the current local clock cycle, such that a second period of the local clock period of the second sequence execution pipeline stages is reduced by a same amount of total additional time margins added to the one or more selected first sequence of control pipeline stages, in order to keep local clock period constant to maintain smooth operations for a next local clock cycle.
9. The dynamic clock management method of claim 1 , wherein the CU is one of a multi-core CUs within a processor, and the execution pipeline stages in each CU executes in-flight instructions independently and out-of-order from each other according to a local clock periods generated by its own on-chip DLL local clock generators.
10. The dynamic clock management method of claim 9 , wherein each CU accesses a same level two (L2) cache memory through a scheduler of an asynchronous memory interface, wherein an on-chip DLL local clock generator of each CU is synchronized to a same on-chip digital phase locked (PLL) global clock according to a hierarchical clock distribution system.