IP Library › Granted Patent US 12,027,648
Granted Patent B2
US 12,027,648 · App. 17/417,493 · Granted Jul 2, 2024

Light-emitting diode chip, display substrate and manufacturing method thereof

Inventors: Junjie Ma (Beijing, CN); Haiwei Sun (Beijing, CN); Yuanda Lu (Beijing, CN); Shanwei Yang (Beijing, CN); Linxia Qi (Beijing, CN); Zhijun Xiong (Beijing, CN); Jiawei Zhao (Beijing, CN)
Assignees: BOE MLED Technology Co., Ltd.; BOE Technology Group Co., Ltd.
H01L33/382H01L25/0753H01L33/005H01L33/62H01L2933/0016H01L2933/0066
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Quick Facts
Patent No.
US 12,027,648
App. No.
17/417,493
Granted
Jul 2, 2024
Kind
B2
Abstract

A light-emitting diode chip, a display substrate and a manufacturing method thereof are disclosed. The light-emitting diode chip includes a first conductive type semiconductor layer, a light-emitting layer, at least two second conductive type semiconductor layers, and at least two first electrodes; the at least two second conductive type semiconductor layers are at a side of the light-emitting layer away from the first conductive type semiconductor layer, the at least two first electrodes are electrically respectively connected with the at least two second conductive type semiconductor layers. Orthographic projections of the at least two second conductive type semiconductor layers on the first conductive type semiconductor layer are spaced apart from each other, and orthographic projections of the at least two first electrodes on the first conductive type semiconductor layer are spaced apart from each other.

Claims (51)

1. A light-emitting diode chip, comprising:

a first conductive type semiconductor layer;

a light-emitting layer at a side of the first conductive type semiconductor layer;

at least two second conductive type semiconductor layers at a side of the light-emitting layer away from the first conductive type semiconductor layer; and

at least two first electrodes electrically respectively connected with the at least two second conductive type semiconductor layers,

wherein orthographic projections of the at least two second conductive type semiconductor layers on the first conductive type semiconductor layer are spaced apart from each other, and orthographic projections of the at least two first electrodes on the first conductive type semiconductor layer are spaced apart from each other,

the light-emitting diode chip further comprises a base substrate, wherein the first conductive type semiconductor layer, the light-emitting layer, and the second conductive type semiconductor layer are sequentially stacked on the base substrate,

the light-emitting layer and the second conductive type semiconductor layer are partially etched to expose the first conductive type semiconductor layer, the light-emitting diode chip further comprises a first insulation layer located on a side of an exposed portion of the first conductive type semiconductor layer away from the base substrate, the first insulation layer is in direct contact with the exposed portion of the first conductive type semiconductor layer,

an orthographic projection of the light-emitting layer on the base substrate is not overlapped with an orthographic projection of the first insulation layer on the base substrate, and an orthographic projection of the first electrode on the base substrate partially overlaps with the orthographic projection of the first insulation layer on the base substrate.

2. The light-emitting diode chip according to claim 1 , further comprising:

a second electrode electrically connected to the first conductive type semiconductor layer,

wherein the second electrode, the first conductive type semiconductor layer, the light-emitting layer, the at least two second conductive type semiconductor layers and the at least two first electrodes constitute at least two light-emitting structures, and the at least two light-emitting structures share the first conductive type semiconductor layer.

3. The light-emitting diode chip according to claim 2 , wherein the second electrode is at a side of the first conductive type semiconductor layer away from the light-emitting layer, and the at least two first electrodes are at a side of the at least two second conductive type semiconductor layers away from the light-emitting layer.

4. The light-emitting diode chip according to claim 2 , wherein both the second electrode and the at least two first electrodes are at a side of the at least two second conductive type semiconductor layers away from the light-emitting layer.

5. The light-emitting diode chip according to claim 4 , wherein the orthographic projections of the at least two first electrodes on the first conductive type semiconductor layer surrounds an orthographic projection of the second electrode on the first conductive type semiconductor layer.

6. The light-emitting diode chip according to claim 1 , wherein a planar shape of the first conductive type semiconductor layer is an N-polygon, and the orthographic projections of the at least two first electrodes on the first conductive type semiconductor layer are respectively on perpendicular bisectors of at least two edges of the N-polygon or on corners of the N-polygon, and the at least two edges are uniformly distributed among all edges of the N-polygon,

an orthographic projection of a second electrode on the first conductive type semiconductor layer is at a center of the N-polygon, and N is a positive integer greater than or equal to 3.

7. The light-emitting diode chip according to claim 1 , wherein a planar shape of the first conductive type semiconductor layer is any one selected from a group consisting of a triangle, a rectangle, a cross shape, a pentagon, a hexagon, and an octagon.

8. The light-emitting diode chip according to claim 1 , wherein a size of the first conductive type semiconductor layer ranges from 3 mil to 5 mil, and a size of the orthographic projection of each of the first electrodes on the first conductive type semiconductor layer is less than 20 microns.

9. A display substrate, comprising:

a substrate; and

a plurality of first light-emitting diode chips on the substrate, wherein each of the plurality of first light-emitting diode chips is the light-emitting diode chip according to claim 1 .

10. The display substrate according to claim 9 , further comprising:

a pixel circuit layer between the substrate and the plurality of first light-emitting diode chips,

wherein the pixel circuit layer comprises a plurality of pixel circuit units, each of the plurality of pixel circuit units comprises a signal output end,

in each of the plurality of first light-emitting diode chips, the at least two first electrodes are respectively connected with the signal output ends of different ones of the plurality of pixel circuit units.

11. The display substrate according to claim 9 , further comprising:

a pixel circuit layer between the substrate and the plurality of first light-emitting diode chips,

wherein the pixel circuit layer comprises a plurality of pixel circuit units, each of the plurality of pixel circuit units comprises a signal output end,

in each of the plurality of first light-emitting diode chips, the at least two first electrodes are respectively connected with the signal output end of a same one of the plurality of pixel circuit units.

12. The display substrate according to claim 9 , further comprising:

a plurality of second light-emitting diode chips on the substrate,

wherein each of the plurality of second light-emitting diode chips is configured to emit light of a first color, and the plurality of first light-emitting diode chips comprise a second color light-emitting diode chip and a third color light-emitting diode chip, the second color light-emitting diode chip is configured to emit light of a second color, and the third color light-emitting diode chip is configured to emit light of a third color, a yield of the second light-emitting diode chip is smaller than a yield of the second color light-emitting diode chip with a same size as the second light-emitting diode chip and smaller than a yield of the third color light-emitting diode chip with the same size as the second light-emitting diode chip.

13. The display substrate according to claim 9 , wherein a planar shape of the first conductive type semiconductor layer is an N-polygon, the orthographic projections of the at least two first electrodes on the first conductive type semiconductor layer are on perpendicular bisectors of at least two edges of the N-polygon or on corners of the N-polygon, the at least two edges are uniformly distributed among all edges of the N-polygon, and an orthographic projection of a second electrode on the first conductive type semiconductor layer is at a center of the N-polygon, and N is a positive integer greater than or equal to 3, and

the plurality of first light-emitting diode chips are arranged in an array along a first direction and a second direction on the substrate.

14. The display substrate according to claim 13 , wherein centers of the first conductive type semiconductor layers of all first light-emitting diode chips arranged in the first direction are approximately on a same straight line.

15. The display substrate according to claim 13 , wherein extension directions of two adjacent edges respectively of two first conductive type semiconductor layers of two adjacent ones of the plurality of first light-emitting diode chips arranged in the first direction are substantially parallel, and a distance between the two adjacent ones of the plurality of first light-emitting diode chips arranged in the first direction is less than 75 microns.

16. The display substrate according to claim 13 , wherein centers of the first conductive type semiconductor layers of the first light-emitting diode chips arranged in the first direction are on different straight lines,

extension directions of two adjacent edges respectively of two first conductive type semiconductor layers of two adjacent ones of the plurality of first light-emitting diode chips arranged in the first direction are approximately parallel, and a distance between the two adjacent ones of the plurality of first light-emitting diode chips arranged in the first direction is less than 75 microns.

17. The display substrate according to claim 9 , further comprising:

a black matrix between adjacent ones of the plurality of the first light-emitting diode chips, wherein the substrate is a glass substrate.

18. The display substrate according to claim 9 , wherein the plurality of first light-emitting diode chips are configured to emit light of a same color.

19. A manufacturing method of the display substrate according to claim 9 , comprising:

manufacturing structure layers of the plurality of first light-emitting diode chips on a base substrate;

splitting the base substrate on which the structure layers of the plurality of first light-emitting diode chips are formed, to form a plurality of first light-emitting diode chips that are separated from each other;

transferring the plurality of first light-emitting diode chips onto the substrate by adopting a transfer process; and

bonding the plurality of first light-emitting diode chips on the substrate by adopting a bonding process.

20. The manufacturing method of the display substrate according to claim 19 , wherein the splitting the base substrate on which the structure layers of the plurality of first light-emitting diode chips are formed, to form the plurality of first light-emitting diode chips that are separated from each other comprises:

adopting an etching process to split the structure layers of the plurality of first light-emitting diode chips to form the plurality of first light-emitting diode chips that are separated from each other, and

the bonding the plurality of first light-emitting diode chips on the substrate by adopting the bonding process comprises:

bonding the plurality of first light-emitting diode chips on the substrate by adopting a reflow soldering process.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2022
From: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
To: BOE MLED TECHNOLOGY CO., LTD.
Reel/Frame 059270/0990 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: MA, JUNJIE; SUN, HAIWEI; LU, YUANDA; YANG, SHANWEI; QI, LINXIA; XIONG, ZHIJUN; ZHAO, JIAWEI
To: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.; BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 056651/0528 →
Continuity (1)
Related Publication 20220336706A1 · Oct 20, 2022
Cited By (1)
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