Display substrate, manufacturing method thereof, and display device

1. A display substrate, wherein in a plane parallel to the display substrate, the display substrate comprises a plurality of sub-pixels, at least one sub-pixel comprises a pixel driving circuit and a light emitting device connected to the pixel driving circuit, the pixel driving circuit at least comprises a storage capacitor, a driving transistor and at least one switching transistor; in a plane perpendicular to the display substrate, the display substrate comprises a semiconductor layer and a plurality of conductive layers; and

a gate electrode of the driving transistor and a gate electrode of the at least one switching transistor are arranged on different conductive layers respectively,

wherein the semiconductor layer is disposed on a base, the plurality of conductive layers comprises a first conductive layer, a second conductive layer and a third conductive layer disposed sequentially on one side of the semiconductor layer away from the base, the gate electrodes of the plurality of switching transistors are arranged on the first conductive layer, and the gate electrode of the driving transistor is arranged on the second conductive layer or the third conductive layer,

wherein the display substrate further comprises a second insulating layer, a third insulating layer and a fourth insulating layer; the second insulating layer covers the semiconductor layer, and the semiconductor layer comprises an active layer of the driving transistor and active layers of the plurality of switching transistors; the first conductive layer is disposed on the second insulating layer and comprises the gate electrodes of the plurality of switching transistors; the third insulating layer covers the first conductive layer, and the second conductive layer is disposed on the third insulating layer and comprises the gate electrode of the driving transistor; and the fourth insulating layer covers the second conductive layer, and the third conductive layer is disposed on the fourth insulating layer and comprises a first power line,

wherein the third conductive layer further comprises a first connecting electrode, a first via hole exposing the gate electrode of the driving transistor is provided in the fourth insulating layer, and a second via hole exposing the active layer of the switching transistor is provided in the second, third and fourth insulating layers; and the first connecting electrode is connected to the gate electrode of the driving transistor through the first via hole and is connected to the active layer of the switching transistor through the second via hole.

2. The display substrate according to claim 1 , wherein

the display substrate further comprises a second insulating layer, a third insulating layer and a fourth insulating layer;

the second insulating layer covers the semiconductor layer, and the semiconductor layer comprises an active layer of a driving transistor and active layers of a plurality of switching transistors;

the first conductive layer is disposed on the second insulating layer, and the first conductive layer comprises gate electrodes of the plurality of switching transistors;

the fourth insulating layer covers the first conductive layer, and the second conductive layer is disposed on the fourth insulating layer and comprises a first power line; and

the third insulating layer covers the second conductive layer, and the third conductive layer is disposed on the third insulating layer and comprises a gate electrode of the driving transistor.

3. The display substrate according to claim 2 , wherein

the second conductive layer further comprises a first connecting electrode, a second via hole exposing the active layer of the switching transistor is provided in the second insulating layer and the fourth insulating layer, and the first connecting electrode is connected to the active layer of the switching transistor through the second via hole; and

a first via hole exposing the first connecting electrode is provided in the third insulating layer, and the gate electrode of the driving transistor is connected to the first connecting electrode through the first via hole.

4. The display substrate according to claim 2 , wherein

a second via hole exposing the active layer of the switching transistor is provided in the second, fourth and third insulating layers, and

the gate electrode of the driving transistor is connected to the active layer of the switching transistor through the second via hole.

5. The display substrate according to claim 4 , wherein

the gate electrode of the driving transistor comprises a first portion, a second portion and a third portion connected sequentially,

the first portion extending along a pixel column direction and being connected to the second portion,

the second portion extending along a pixel row direction and being connected to the third portion, and

the third portion extending along the pixel column direction.

6. The display substrate according to claim 5 , wherein

there is an overlapping area between an orthographic projection of the first portion on the base and an orthographic projection of the first power line on the base, and

there is an overlapping area between an orthographic projection of the third portion on the base and an orthographic projection of the active layer of the driving electrode on the base.

7. The display substrate according to claim 1 , wherein

there is an overlapping area between an orthogonal projection of the gate electrode of the driving transistor on the base and an orthogonal projection of the first power line on the base,

the gate electrode of the driving transistor in the overlapping area serves as a first polar plate of the storage capacitor, and

the first power line in the overlapping area serves as a second polar plate of the storage capacitor.

8. The display substrate according to claim 1 , wherein the first conductive layer comprises a first scanning signal line, a second scanning signal line and a light emitting control line.

9. The display substrate according to claim 1 , wherein the display substrate further comprises a fifth insulating layer coving the third conductive layer and a fourth conductive disposed on the fifth insulating layer, and

the fourth conductive layer comprising an initial signal line and an anode of the light emitting device.

10. The display substrate according to claim 1 , wherein the area of the gate electrode of the driving transistor is 1 to 10 times the area of the gate electrode the at least one switching transistor.

11. A display device comprising the display substrate according to claim 1 .

12. The display substrate according to claim 1 , wherein the first conductive layer comprises a first scanning signal line, a second scanning signal line and a light emitting control line.

13. The display substrate according to claim 1 , wherein the display substrate further comprises a fifth insulating layer coving the third conductive layer and a fourth conductive disposed on the fifth insulating layer, and

the fourth conductive layer comprising an initial signal line and an anode of the light emitting device.

14. A method for manufacturing a display substrate, wherein in a plane parallel to the display substrate, the display substrate comprises a plurality of sub-pixels, at least one sub-pixel comprises a pixel driving circuit and a light emitting device connected to the pixel driving circuit, and the pixel driving circuit at least comprises a storage capacitor, a driving transistor and at least one switching transistor; the method comprises:

forming a semiconductor layer and a plurality of conductive layers on a base, a gate electrode of the driving transistor and a gate electrode of the at least one switching transistor being arranged on different conductive layers respectively,

wherein forming the semiconductor layer and the plurality of conductive layers on the base comprises:

forming the semiconductor layer on the base;

forming a second insulating layer covering the semiconductor layer and a first conductive layer disposed on the second insulating layer, the first conductive layer comprising the gate electrode of the at least one switching transistor;

forming a third insulating layer covering the first conductive layer and a second conductive layer disposed on the third insulating layer, the second conductive layer comprising the gate electrode of the driving transistor; and

forming a fourth insulating layer covering the second conductive layer and a third conductive layer disposed on the fourth insulating layer, the third conductive layer comprising a first power line and a first connecting electrode; wherein a first via hole exposing the gate electrode of the driving transistor is provided in the fourth insulating layer, a second via hole exposing the active layer of the switching transistor is provided in the second, third and fourth insulating layers, and the first connecting electrode is connected to the gate electrode of the driving transistor through the first via hole and is connected to the active layer of the switching transistor through the second via hole; there is an overlapping area between an orthogonal projection of the gate electrode of the driving transistor on the base and an orthogonal projection of the first power line on the base, the gate electrode of the driving transistor in the overlapping area serves as a first polar plate of the storage capacitor, and the first power line in the overlapping area serves as a second polar plate of the storage capacitor.

15. The method according to claim 14 , wherein forming the semiconductor layer and the plurality of conductive layers on the base comprises:

forming the semiconductor layer on the base;

forming a second insulating layer covering the semiconductor layer and a first conductive layer disposed on the second insulating layer, the first conductive layer comprising the gate electrode of the at least one switching transistor;

forming a fourth insulating layer covering the first conductive layer and a second conductive layer disposed on the fourth insulating layer, wherein the second conductive layer comprises a first power line and a first connecting electrode; a second via hole exposing the active layer of the switching transistor is provided in the second and fourth insulating layers, and the first connecting electrode is connected to the active layer of the switching transistor through the second via hole; and

forming a third insulating layer covering the second conductive layer and a third conductive layer disposed on the third insulating layer, wherein the third conductive layer comprises the gate electrode of the driving transistor; a first via hole exposing the first connecting electrode is provided in the third insulating layer, and the gate electrode of the driving transistor is connected to the first connecting electrode through the first via hole; there is an overlapping area between an orthogonal projection of the gate electrode of the driving transistor on the base and an orthogonal projection of the first power line on the base, the gate electrode of the driving transistor in the overlapping area serves as a first polar plate of the storage capacitor, and the first power line in the overlapping area serves as a second polar plate of the storage capacitor.

16. The method according to claim 14 , wherein forming the semiconductor layer and the plurality of conductive layers on the base comprises:

forming the semiconductor layer on the base;

forming a second insulating layer covering the semiconductor layer and a first conductive layer disposed on the second insulating layer, the first conductive layer comprising the gate electrode of the at least one switching transistor;

forming a fourth insulating layer covering the first conductive layer and a second conductive layer disposed on the fourth insulating layer, wherein the second conductive layer comprises a first power line; and

forming a third insulating layer covering the second conductive layer and a third conductive layer disposed on the third insulating layer, wherein the third conductive layer comprises the gate electrode of the driving transistor; a second via hole exposing the active layer of the switching transistor is provided in the second, fourth and third insulating layers, and the gate electrode of the driving transistor is connected to the active layer of the switching transistor through the second via hole; there is an overlapping area between an orthogonal projection of the gate electrode of the driving transistor on the base and an orthogonal projection of the first power line on the base, the gate electrode of the driving transistor in the overlapping area serves as a first polar plate of the storage capacitor, and the first power line in the overlapping area serves as a second polar plate of the storage capacitor.