Semiconductor device and operating method of semiconductor device
A battery control circuit having a novel structure, a battery protection circuit having a novel structure, and a power storage device including the battery circuit are provided. A semiconductor device includes n cell balancing circuits that respectively correspond to one secondary battery and each include a transistor, a comparator circuit, and a capacitor. In each of the n cell balancing circuits, an inverting input terminal of the comparator circuit and one electrode of the capacitor are electrically connected to one of a source and a drain of the transistor. The semiconductor device has functions of supplying a ground potential to the other electrode of the capacitor; turning on the transistor; supplying a first potential to the one electrode of the capacitor; turning off the transistor; electrically connecting the other electrode of the capacitor and a negative electrode of the secondary battery corresponding to each cell balancing circuit; supplying a sum of the first potential and a potential of the negative electrode of the secondary battery corresponding to each cell balancing circuit, to the one electrode of the capacitor; and controlling charging of the secondary battery corresponding to each cell balancing circuit.
1. A semiconductor device comprising:
a first comparator circuit configured to output a first signal controlling charging of a secondary battery;
a second comparator circuit configured to output a second signal controlling charging of the secondary battery;
a third comparator circuit configured to output a third signal controlling discharging of the secondary battery;
a first transistor of which one of a source electrode and a drain electrode is electrically connected to an inverting input terminal of the first comparator circuit;
a first capacitor of which one electrode is electrically connected to the one of the source electrode and the drain electrode of the first transistor;
a second transistor of which one of a source electrode and a drain electrode is electrically connected to an inverting input terminal of the second comparator circuit;
a second capacitor of which one electrode is electrically connected to the one of the source electrode and the drain electrode of the second transistor;
a third transistor of which one of a source electrode and a drain electrode is electrically connected to a non-inverting input terminal of the third comparator circuit;
a third capacitor of which one electrode is electrically connected to the one of the source electrode and the drain electrode of the third transistor; and
a selector circuit of which an output terminal is electrically connected to the other electrode of the first capacitor, the other electrode of the second capacitor, and the other electrode of the third capacitor,
wherein the other of the source electrode and the drain electrode of the first transistor, the other of the source electrode and the drain electrode of the second transistor, and the other of the source electrode and the drain electrode of the third transistor are electrically connected to one another, and
wherein a first input terminal of the selector circuit is electrically connected to a negative electrode terminal for the secondary battery.
2. The semiconductor device according to claim 1 , wherein each of a non-inverting input terminal of the first comparator circuit, a non-inverting input terminal of the second comparator circuit, and an inverting input terminal of the third comparator circuit is electrically connected to a positive electrode terminal for the secondary battery.
3. The semiconductor device according to claim 1 , wherein a second input terminal of the selector circuit is electrically connected to a terminal having a ground potential.
4. The semiconductor device according to claim 1 , wherein each channel formation region of the first transistor, the second transistor and the third transistor comprises a metal oxide containing indium.
5. The semiconductor device according to claim 1 , further comprising a fourth transistor,
wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to a positive electrode terminal for the secondary battery,
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the negative electrode terminal for the secondary battery, and
wherein a gate electrode of the fourth transistor is electrically connected to an output terminal of the first comparator circuit.
6. The semiconductor device according to claim 1 ,
wherein the semiconductor device comprises n cell balancing circuits,
wherein one of the n cell balancing circuits comprises the first comparator circuit, the second comparator circuit, the third comparator circuit, the first transistor, the first capacitor, the second transistor, the second capacitor, the third transistor, the third capacitor, and the selector circuit, and
wherein each of the n cell balancing circuits has the same circuit structure as the one of the n cell balancing circuits.
7. A semiconductor device comprising:
a first comparator circuit configured to output a first signal controlling charging of a secondary battery;
a first transistor of which one of a source electrode and a drain electrode is electrically connected to an inverting input terminal of the first comparator circuit;
a first capacitor of which one electrode is electrically connected to the one of the source electrode and the drain electrode of the first transistor; and
a first selector circuit of which an output terminal is electrically connected to the other electrode of the first capacitor,
wherein a first input terminal of the first selector circuit is electrically connected to a negative electrode terminal for the secondary battery,
wherein a second input terminal of the first selector circuit is electrically connected to a terminal having a ground potential, and
wherein a non-inverting terminal of the first comparator circuit is electrically connected to a positive electrode terminal for the secondary battery.
8. The semiconductor device according to claim 7 , further comprising:
a second comparator circuit configured to output a second signal controlling the secondary battery;
a third comparator circuit configured to output a third signal controlling discharging of the secondary battery;
a second transistor of which one of a source electrode and a drain electrode is electrically connected to an inverting input terminal of the second comparator circuit;
a second capacitor of which one electrode is electrically connected to the one of the source electrode and the drain electrode of the first transistor;
a third transistor of which one of a source electrode and a drain electrode is electrically connected to a non-inverting input terminal of the third comparator circuit; and
a third capacitor of which one electrode is electrically connected to the one of the source electrode and the drain electrode of the third transistor,
wherein the other of the source electrode and the drain electrode of the first transistor, the other of the source electrode and the drain electrode of the second transistor, and the other of the source electrode and the drain electrode of the third transistor are electrically connected to one another.
9. The semiconductor device according to claim 8 , further comprising a second selector circuit,
wherein an output terminal of the second selector circuit is electrically connected to the other electrode of the second capacitor and the other electrode of the third capacitor.
10. The semiconductor device according to claim 8 , further comprising a fourth transistor,
wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to the positive electrode terminal for the secondary battery,
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the negative electrode terminal for the secondary battery, and
wherein a gate electrode of the fourth transistor is electrically connected to an output terminal of the first comparator circuit.
11. The semiconductor device according to claim 7 , wherein a channel formation region of the first transistor comprises a metal oxide containing indium.
12. The semiconductor device according to claim 7 ,
wherein the semiconductor device comprises n cell balancing circuits,
wherein one of the n cell balancing circuits comprises the first comparator circuit, the first transistor, the first capacitor, and the first selector circuit, and
wherein each of the n cell balancing circuits has a same circuit structure as the one of the n cell balancing circuits.
13. An operating method of a semiconductor device comprising the steps of:
providing a ground potential to one electrode of a capacitor in which the other electrode is electrically connected to an inverting input terminal of a first comparator circuit;
turning on a first transistor in which one of a source electrode and a drain electrode is electrically connected to the other electrode of the capacitor after providing the ground potential;
turning off the first transistor after turning on the first transistor;
electrically connecting the one electrode of the capacitor to a negative electrode of a first secondary battery after turning off the first transistor; and
turning on a second transistor after electrically connecting the one electrode of the capacitor,
wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a positive electrode of the first secondary battery,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the negative electrode of the first secondary battery,
wherein a gate electrode of the second transistor is electrically connected to an output terminal of the first comparator circuit, and
wherein turning on the second transistor is performed by changing a potential of the output terminal of the first comparator circuit.
14. The operating method of a semiconductor device, according to claim 13 , wherein the positive electrode of the first secondary battery is electrically connected to a non-inverting input terminal of the first comparator circuit.
15. The operating method of a semiconductor device, according to claim 13 ,
wherein the capacitor, the first comparator circuit, the first transistor, and the second transistor form a first cell balancing circuit,
wherein the semiconductor device comprises a plurality of cell balancing circuits, and
wherein the first cell balancing circuit is one of the plurality of cell balancing circuits.
16. The operating method of a semiconductor device, according to claim 13 ,
wherein the semiconductor device further comprises a second comparator circuit, a second capacitor, a third transistor, a third comparator circuit, a third capacitor and a fourth transistor,
wherein one electrode of the second capacitor is electrically connected to an inverting input terminal of the second comparator circuit and one of a source electrode and a drain electrode of the third transistor,
wherein one electrode of the third capacitor is electrically connected to a non-inverting input terminal of the third comparator circuit and one of a source electrode and a drain electrode of the fourth transistor, and
wherein in the step of turning off the first transistor, the third transistor and the fourth transistor is turned off.
17. The operating method of a semiconductor device, according to claim 13 ,
wherein a first potential is supplied to the one electrode of the capacitor in the step of turning on the first transistor, and
wherein a sum of the first potential and a potential of the negative electrode of the first secondary battery is supplied to the inverting input terminal of the first comparator circuit in the step of electrically connecting the one electrode of the capacitor.