Methods for protecting computer hardware from cyber threats
A semiconductor intellectual property (IP) core comprising a transformation engine designed and configured to represent each element of a field GF(2 8 ) using a polynomial of degree no higher than 7+d, where d>0 is a redundancy parameter. Also disclosed in the specification are several other IP cores and several different methods.
1. A semiconductor intellectual property (IP) core comprising a transformation engine designed and configured to represent each element of a field GF(2 8 ) using a polynomial of degree no higher than 7+d, where d>0 is a redundancy parameter;
wherein said transformation engine represents a same field element by one of 2 d various ways (pairwise differing by terms that are multiples of P(x)), and at each moment of calculations chooses any of said various representations.
2. An IP core according to claim 1 , wherein d≥9.
3. An IP core according to claim 2 , wherein d≥24.
4. A method of building different representations of the Galois Field (GF) implemented by logic circuitry comprising:
representing each element of a field GF(2 8 ) using a polynomial of degree no higher than 7+d, where d>0 is a redundancy parameter; and
representing a same field element by one of 2 d various ways (pairwise differing by terms that are multiples of P(x)), and at each moment of calculations chooses any of said various representations.
5. A method according to claim 4 , wherein d≥9.
6. A method according to claim 5 , wherein d≥24.
7. An IP core according to claim 1 , wherein said element of a field comprises a byte of data within a block of a block cipher and a cryptographic key.
8. An IP core according to claim 7 , wherein said block cipher is selected from the group consisting of AES, SM4, and ARIA.
9. An IP core according to claim 1 , wherein said transformation engine computes X Y by performing a series of:
(i) multiplications of two different elements of the field; and
(ii) raising an element of the field to a power Z wherein Z is a power of 2;
wherein the number of multiplications (i) is at least two less than the number of ones (1s) in the binary representation of Y.
10. An IP core according to claim 9 , wherein Y=254.
11. An IP core according to claim 10 , wherein a number of multiplications (i) is 4 or less.
12. A method according to claim 4 , wherein said element of a field comprises a byte of data within a block of a block cipher and a cryptographic key.
13. A method according to claim 12 , wherein said block cipher is selected from the group consisting of AES, SM4, and ARIA.
14. A method according to claim 4 , comprising computing X Y by performing a series of:
(i) multiplications of two different elements of the field; and
(ii) raising an element of the field to a power Z wherein Z is a power of 2;
wherein the number of multiplications (i) is at least two less than the number of ones (1s) in the binary representation of Y.
15. A method according to claim 14 , wherein Y=254.
16. A method according to claim 15 , wherein a number of multiplications (i) is 4 or less.