Shift register for outputting hybrid pulses for display and compensation and driving method therefor, gate driving circuit, and display panel

1. A shift register, wherein the shift register comprises:

a display control circuit connected to a pull-up node, a first power terminal and a first control terminal, and configured to write a potential, provided by the first power terminal, into the pull-up node in a display mode under the control of the first control terminal;

a sensing control circuit connected to the pull-up node, a second control terminal and a third control terminal, and configured to store the potential of the pull-up node in the display mode under the control of the second control terminal and write the stored potential into the pull-up node in a sensing mode under the control of the third control terminal; and

a first output circuit connected to the pull-up node, a first clock terminal and a first output terminal, and configured to supply a first clock signal of the first clock terminal to the first output terminal under the control of the potential of the pull-up node;

wherein the sensing control circuit comprises:

a sensing input sub-circuit connected to the pull-up node, a hold node, and the second control terminal, and configured to store the potential of the pull-up node in the hold node under the control of the second control terminal; and

a sensing pull-up sub-circuit connected to the pull-up node, the hold node and the third control terminal, and configured to write the potential, stored in the hold node, into the pull-up node in the sensing mode under the control of the third control terminal;

wherein the sensing input sub-circuit comprises:

a first transistor having a first pole connected to the pull-up node, a second pole connected to the hold node, and a control pole connected to the second control terminal; and

a first capacitor having a terminal directly connected to the hold node and a terminal directly connected to a second power terminal.

2. The shift register according to claim 1 , wherein the sensing pull-up sub-circuit comprises:

a second transistor having a first pole connected to the hold node, a second pole connected to the pull-up node, and a control pole connected to the third control terminal.

3. The shift register according to claim 1 , wherein the first output circuit comprises:

a third transistor having a first pole connected to the first clock terminal, a second pole connected to the first output terminal, and a control pole connected to the pull-up node; and

a second capacitor having a terminal connected to the control pole of the third transistor and a terminal connected to the second pole of the third transistor.

4. The shift register according to claim 1 , wherein the shift register further comprises:

a cascade output circuit connected to a second clock terminal, the pull-up node and a cascade output terminal, and configured to supply a second clock signal of the second clock terminal to the cascade output terminal under the control of the potential of the pull-up node.

5. The shift register according to claim 4 , wherein the cascade output circuit comprises:

a fourth transistor having a first pole connected to the second clock terminal, a second pole connected to the cascade output terminal, and a control pole connected to the pull-up node.

6. The shift register according to claim 4 , wherein the display control circuit comprises:

an input sub-circuit connected to the pull-up node, the first power terminal and the first control terminal, and configured to write the potential, provided by the first power terminal, into the pull-up node in the display mode under the control of the first control terminal;

a discharge sub-circuit connected to the pull-up node, a second power terminal and a discharge control terminal, and configured to discharge the pull-up node to a potential of the second power terminal according to a discharge control signal of the discharge control terminal;

a pull-down control sub-circuit connected to the pull-up node, a pull-down node, the first power terminal and the second power terminal, and configured to control a potential of the pull-down node by means of the potential of the first power terminal and the potential of the second power terminal under the control of the pull-up node;

a first pull-down sub-circuit connected to the pull-down node, the pull-up node, the cascade output terminal and the second power terminal, and configured to pull the pull-up node and the cascade output terminal down to the potential of the second power terminal under the control of the pull-down node;

a second pull-down sub-circuit connected to the pull-down node, the first output terminal and a third power terminal, and configured to pull the first output terminal down to a potential of the third power terminal under the control of the pull-down node; and

a reset sub-circuit connected to a reset control terminal, the pull-up node and the second power terminal, and configured to reset the pull-up node to the potential of the second power terminal under the control of the reset control terminal.

7. The shift register according to claim 6 , wherein the input sub-circuit comprises: a fifth transistor having a first pole connected to the first power terminal, a second pole connected to the pull-up node, and a control pole connected to the first control terminal.

8. The shift register according to claim 6 , wherein the discharge sub-circuit comprises: a sixth transistor having a first pole connected to the pull-up node, a second pole connected to the second power terminal, and a control pole connected to the discharge control terminal.

9. The shift register according to claim 6 , wherein the pull-down control sub-circuit comprises: a seventh transistor and an eighth transistor, wherein a control pole and a first pole of the seventh transistor are both connected to the first power terminal, a second pole of the seventh transistor and a first pole of the eighth transistor are connected to the pull-down node, a control pole of the eighth transistor is connected to the pull-up node, and a second pole of the eighth transistor is connected to the second power terminal.

10. The shift register according to claim 6 , wherein the first pull-down sub-circuit comprises: a ninth transistor and a tenth transistor, wherein a first pole of the ninth transistor is connected to the pull-up node, a second pole of the ninth transistor is connected to the second power terminal, a control pole of the ninth transistor is connected to the pull-down node, a first pole of the tenth transistor is connected to the cascade output terminal, a second pole of the tenth transistor is connected to the second power terminal, and a control pole of the tenth transistor is connected to the pull-down node.

11. The shift register according to claim 6 , wherein the second pull-down sub-circuit comprises: an eleventh transistor having a first pole connected to the first output terminal, a second pole connected to the third power terminal, and a control pole connected to the pull-down node.

12. The shift register according to claim 6 , wherein the reset sub-circuit comprises: a twelfth transistor having a first pole connected to the pull-up node, a second pole connected to the second power terminal, and a control pole connected to the reset control terminal.

13. A gate drive circuit, wherein the gate drive circuit comprises N levels of cascaded shift registers according to claim 1 , wherein N is an integer greater than 1.

14. The gate drive circuit according to claim 13 , wherein the first control terminal of an nth level of shift register is connected to a cascade output terminal of a (n−2)th level of shift register, and a discharge control terminal of the nth level of shift register is connected to a cascade output terminal of a (n+3)th level of shift register, wherein n is an integer, and 3≤n≤N−3.

15. A display panel, wherein the display panel comprises the gate drive circuit according to claim 13 .

16. A drive method of the shift register according to claim 1 , wherein the method comprises:

in the display mode, writing, by the display control circuit under the control of the first control terminal, the potential provided by the first power terminal into the pull-up node, storing, by the sensing control circuit under the control of the second control terminal, the potential of the pull-up node, and supplying, by the first output circuit under the control of the potential of the pull-up node, the first clock signal of the first clock terminal to the first output terminal; and

in the sensing mode, writing, by the sensing control circuit under the control of the third control terminal, the stored potential into the pull-up node, and supplying, by the first output circuit under the control of the potential of the pull-up node, the first clock signal of the first clock terminal to the first output terminal.

17. The gate drive circuit according to claim 13 , wherein the sensing control circuit comprises:

a sensing input sub-circuit connected to the pull-up node, a hold node, and the second control terminal, and configured to store the potential of the pull-up node in the hold node under the control of the second control terminal; and

a sensing pull-up sub-circuit connected to the pull-up node, the hold node and the third control terminal, and configured to write the potential, stored in the hold node, into the pull-up node in the sensing mode under the control of the third control terminal.

18. The gate drive circuit according to claim 17 , wherein the sensing input sub-circuit comprises:

a first transistor having a first pole connected to the pull-up node, a second pole connected to the hold node, and a control pole connected to the second control terminal; and

a first capacitor having a terminal connected to the hold node and a terminal connected to a second power terminal.