IP Library Granted Patent US 12,066,975
Granted Patent B2
US 12,066,975 · App. 17/429,291 · Granted Aug 20, 2024

Cache structure and utilization

Inventors: Altug Koker (El Dorado Hills, CA); Lakshminarayanan Striramassarma (Folsom, CA); Aravindh Anantaraman (Folsom, CA); Valentin Andrei (San Jose, CA); Abhishek R. Appu (El Dorado Hills, CA); Sean Coleman (Folsom, CA); Varghese George (Folsom, CA); K Pattabhiraman (Bangalore KA, IN); Mike MacPherson (Portland, OR); Subramaniam Maiyuran (Gold River, CA); ElMoustapha Ould-Ahmed-Vall (Chandler, AZ); Vasanth Ranganathan (El Dorado Hills, CA); Joydeep Ray (Folsom, CA); S Jayakrishna P (Bangalore KA, IN); Prasoonkumar Surti (Folsom, CA)
Assignee: INTEL CORPORATION
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Quick Facts
Patent No.
US 12,066,975
App. No.
17/429,291
Granted
Aug 20, 2024
Kind
B2
Abstract

Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.

Claims (38)

1. An apparatus comprising:

one or more processors including a graphics processing unit (GPU); and

a memory for storage of data for processing by the one or more processors;

wherein the GPU includes a GPU cache to cache data from the memory for use by the GPU;

wherein the apparatus is to provide for dynamic overfetching of cache lines for the GPU cache, including:

dynamically selecting an overfetch boundary to be applied for one or more received read requests for the GPU,

receiving a read request requesting data for the GPU and accessing the GPU cache for the requested data, and

upon a miss in the GPU cache, overfetching data from memory or a higher level cache to the GPU cache in addition to fetching the requested data;

wherein the overfetching of data is based at least in part on the selected overfetch boundary for the one or more read requests, and provides for data is to be prefetched extending to the selected overfetch boundary; and

wherein the apparatus is further to provide for eviction of data from the GPU cache with the selected overfetch boundary being maintained for the eviction, including, upon a determination that the requested data is to be evicted from the GPU cache, further evicting the overfetched data from the GPU cache according to the selected overfetch boundary applied for the one or more read requests.

2. The apparatus of claim 1 , wherein the dynamic selection of the overfetch boundary for the one or more read requests is based on data accesses that are being performed for the one or more read requests.

3. The apparatus of claim 1 , wherein the dynamic selection of the overfetch boundary for the one or more read requests is based on a type of data compression that is being utilized for the memory.

4. The apparatus of claim 1 , wherein the overfetch boundary is selected from a plurality of possible overfetch boundaries.

5. The apparatus of claim 4 , wherein the plurality of possible overfetch boundaries include a 512 B sector boundary and a 1 KB sector boundary.

6. The apparatus of claim 1 , wherein the dynamically selected overfetch boundary modifies one of either a default overfetch boundary or an initial setting overfetch boundary.

7. The apparatus of claim 1 , wherein the GPU cache is one of an L2 cache or an L3 cache.

8. One or more non-transitory computer-readable storage mediums having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:

dynamically selecting an overfetch boundary to be applied for one or more received read requests for a graphics processing unit (GPU), the GPU including a GPU cache to cache data from a memory for use by the GPU;

receiving a read request requesting data for the GPU;

accessing the GPU cache for the requested data; and

upon a miss in the GPU cache, overfetching data from a memory or a higher level cache to the GPU cache in addition to fetching the requested data;

wherein the overfetching of data is based at least in part on the selected overfetch boundary for the one or more read requests, and provides for data is to be prefetched extending to the selected overfetch boundary; and

wherein data is further to be evicted from the GPU cache with the selected overfetch boundary being maintained for the eviction, including, upon a determination that the requested data is to be evicted from the GPU cache, the overfetched data is further evicted from the GPU cache according to the selected overfetch boundary for the one or more read requests.

9. The one or more computer-readable storage mediums of claim 8 , wherein the dynamic selection of the overfetch boundary for the one or more read requests is based on data accesses that are being performed for the one or more read requests.

10. The one or more computer-readable storage mediums of claim 8 , wherein the dynamic selection of the overfetch boundary for the one or more read requests is based on a type of data compression that is being utilized for the memory.

11. The one or more computer-readable storage mediums of claim 9 , wherein the overfetch boundary is selected from a plurality of possible overfetch boundaries.

12. The one or more computer-readable storage mediums of claim 11 , wherein the plurality of possible overfetch boundaries include a 512 B sector boundary and a 1 KB sector boundary.

13. The one or more computer-readable storage mediums of claim 8 , wherein the selected overfetch boundary modifies one of either a default overfetch boundary or an initial setting overfetch boundary.

14. A method comprising:

dynamically selecting an overfetch boundary to be applied for one or more received read requests for a graphics processing unit (GPU), the GPU including a GPU cache to cache data from a memory for use by the GPU;

receiving a read request requesting data for the GPU;

accessing the GPU cache for the requested data; and

upon a miss in the GPU cache, overfetching data from a memory or a higher level cache to the GPU cache in addition to fetching the requested data;

wherein the overfetching of data is based at least in part on the selected overfetch boundary for the one or more read requests, and provides for data is to be prefetched extending to the selected overfetch boundary; and

wherein data is further to be evicted from the GPU cache with the selected overfetch boundary being maintained for the eviction, including, upon a determination that the requested data is to be evicted from the GPU cache, the overfetched data is further evicted from the GPU cache according to the selected overfetch boundary for the one or more read requests.

15. The method of claim 14 , wherein the dynamic selection of the overfetch boundary for the one or more read requests is based on data accesses that are being performed for the one or more read requests.

16. The method of claim 14 , wherein the dynamic selection of the overfetch boundary for the one or more read requests is based on a type of data compression that is being utilized for the memory.

17. The method of claim 14 , wherein the overfetch boundary is selected from a plurality of possible overfetch boundaries.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 6, 2021
From: KOKER, ALTUG; STRIRAMASSARMA, LAKSHMINARAYANAN; ANANTARAMAN, ARAVINDH; ANDREI, VALENTIN; APPU, ABHISHEK R.; COLEMAN, SEAN; GEORGE, VARGEHESE; PATTABHIRAMAN, K; MACPHERSON, MIKE; MAIYURAN, SUBRAMANIAM; OULD-AHMED-VALL, ELMOUSTAPHA; RANGANATHAN, VASANTH; RAY, JOYDEEP; JAYAKRISHNA P, S; SURTI, PRASOONKUMAR
To: INTEL CORPORATION
Reel/Frame 057110/0483 →
Continuity (4)
Provisional Application 62819337 · Mar 15, 2019
Provisional Application 62819435 · Mar 15, 2019
Provisional Application 62819361 · Mar 15, 2019
Related Publication 20220138104A1 · May 5, 2022
Cited By (3)
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