Test circuits and semiconductor test methods
The present application relates to a test circuit, comprising: M stages of test units, first terminals of test units in each stage being all connected to a power wire, second terminals of test units in each stage being all connected to a ground wire, third terminals of test units in the first stage being connected to the power wire, and third terminals of test units in the i th stage being connected to fourth terminals of test units in the (i−1) th stage; wherein, the M and i are positive integers greater than or equal to 2.
1. A test circuit, comprising:
M stages of test units, the test unit in each stage having a first terminal, a second terminal, a third terminal, and a fourth terminal, the first terminal of the test unit in each stage being connected to a power wire, the second terminal of the test unit in each stage being connected to a ground wire, the third terminal of the test unit in a first stage of the stages being connected to the power wire, and the third terminal of the test unit in an i th stage of the stages being connected to the fourth terminal of the test unit in an (i−1) th stage of the stages; wherein, the M and the i are positive integers greater than or equal to 2;
wherein the test unit in each stage comprises an electro-migration test element, a switch, and a control circuit, wherein a first terminal of the electro-migration test element is the first terminal of the test unit, a second terminal of the electro-migration test element is connected to a first terminal of the switch and a first terminal of the control circuit, a control terminal of the switch is the third terminal of the test unit, a second terminal of the switch is the second terminal of the test unit, and a second terminal of the control circuit is the fourth terminal of the test unit.
2. The test circuit according to claim 1 , wherein the electro-migration test element has a first equivalent resistance before being burned, the electro-migration test element has a second equivalent resistance after being burned, and the first equivalent resistance is less than the second equivalent resistance.
3. The test circuit according to claim 2 , wherein a ratio of the second equivalent resistance to the first equivalent resistance is greater than or equal to 100.
4. The test circuit according to claim 1 , wherein a length of the electro-migration test element is 10 μm to 20000 μm.
5. The test circuit according to claim 1 , wherein lengths of the electro-migration test elements in the test units in all stages are the same, and widths of the electro-migration test elements in the test units in all stages are the same.
6. The test circuit according to claim 1 , wherein lengths of the electro-migration test elements in the test units in all stages are different, and widths of the electro-migration test elements in the test units in all stages are the same.
7. The test circuit according to claim 1 , wherein lengths of the electro-migration test elements in the test units in all stages are different, and widths of the electro-migration test elements in the test units in all stages are different.
8. The test circuit according to claim 1 , wherein the electro-migration test element comprises a metal wire.
9. The test circuit according to claim 1 , wherein the switch comprises an n-type metal-oxide semiconductor (NMOS) transistor, and a gate, a drain, and a source of the NMOS transistor correspond to the control terminal, the first terminal, and the second terminal of the switch, respectively.
10. The test circuit according to claim 1 , wherein the control circuit comprises an inverter, and an input terminal and an output terminal of the inverter correspond to the first terminal and the second terminal of the control circuit, respectively.
11. A semiconductor test method, comprising:
connecting the power wire in the test circuit according to claim 1 to a power supply device outside a chip;
monitoring changes in voltage and current of the power supply device; and
obtaining lifetimes of all the electro-migration test elements according to the monitored voltage and current.
12. The semiconductor test method according to claim 11 , wherein change in current of the electro-migration test element ranges from 1×10 5 A/cm 2 to 1×10 10 A/cm 2 .