Granted Patent B2

US 12,450,001 · App. 17/435,167 · Granted Oct 21, 2025

Inventors: Connor Hann (New Haven, CT); Changling Zou (New Haven, CT); Yiwen Chu (New Haven, CT); Yaxing Zhang (New Haven, CT); Robert J. Schoelkopf, III (Madison, CT); Steven M. Girvin (Hamden, CT); Liang Jiang (Guilford, CT)

Assignee: Yale University

G06F3/0655G06F3/0604G06F3/0679G06N10/20G06N10/40G06N10/60

Abstract

Claims (33)

1 . A method of accessing a memory using a quantum address by operating a quantum router, the quantum router comprising a superconducting circuit coupled to a bosonic system, the bosonic system exhibiting non-uniformity in a frequency spacing of at least some modes of the bosonic system, the method comprising:

initializing a plurality of address qubits with values based on the quantum address, wherein each of the plurality of address qubits is represented by a respective mode of the bosonic system;

initializing a plurality of register qubits, wherein each of the plurality of register qubits is represented by a respective mode of the bosonic system;

performing a plurality of quantum gates by providing energy to the superconducting circuit, each quantum gate changing a state of at least one of the plurality of register qubits based at least in part on a state of one of the plurality of address qubits; and

performing, by providing energy to the superconducting circuit, a phase shift of one or more of the plurality of register qubits according to values stored in the memory.

2 . The method of claim 1 , wherein the memory is a classical memory storing a plurality of bits.

3 . The method of claim 2 , further comprising, for each bit of the plurality of bits stored in the memory, determining, based on a value of the bit, whether or not to perform a phase shift of a register qubit associated with the bit.

4 . The method of claim 1 , further comprising performing a second plurality of quantum gates subsequent to performing the phase shift of the one or more of the plurality of register qubits, the second plurality of quantum gates being based on states of one or more of the plurality of phase-shifted register qubits.

5 . The method of claim 1 , wherein initializing a plurality of register qubits comprises initializing one of the plurality of register qubits with a bus value, and initializing a remainder of the plurality of register qubits to a same state as one another.

6 . The method of claim 1 , wherein performing each quantum gate of the plurality of quantum gates comprises driving the superconducting circuit with two or more drives of different frequencies selected based on frequencies of modes of the bosonic system.

7 . The method of claim 1 , wherein performing the plurality of quantum gates by providing energy to the superconducting circuit comprises performing a plurality of SWAP gates.

8 . The method of claim 1 , wherein performing the plurality of quantum gates by providing energy to the superconducting circuit comprises performing a plurality of CZ gates.

9 . The method of claim 1 , wherein performing the plurality of quantum gates by providing energy to the superconducting circuit comprises performing one or more of the plurality of quantum gates in a series of time steps, wherein a number of time steps in the series of time steps is of order log 2 (N), wherein N is a number of bits stored by the memory.

10 . The method of claim 1 , wherein the bosonic system comprises a crystal resonator.

11 . The method of claim 1 , wherein the memory is a quantum memory storing a plurality of qubits.

12 . A quantum random access memory (QRAM) system, comprising:

a memory;

a quantum router comprising:

a superconducting circuit comprising at least one non-linear element; and

a bosonic system coupled to the superconducting circuit, the bosonic system exhibiting non-uniformity in a frequency spacing of at least some modes of the bosonic system; and

at least one controller configured to manipulate states of modes of the bosonic system by applying energy to the superconducting circuit based on a quantum address representing a superposition of address locations within the memory.

13 . The QRAM system of claim 12 , wherein the bosonic system comprises a crystal resonator.

14 . The QRAM system of claim 13 , wherein the crystal resonator is a bulk acoustic wave (BAW) resonator or a surface acoustic wave (SAW) resonator.

15 . The QRAM system of claim 12 , wherein the superconducting circuit comprises a transmon qubit.

16 . The QRAM system of claim 12 , further comprising a transducer coupling the superconducting circuit to the bosonic system.

17 . The QRAM system of claim 16 , wherein the transducer comprises piezoelectric material.

18 . The QRAM system of claim 12 , wherein the at least one controller is configured to:

initialize a plurality of address qubits with values based on the quantum address, wherein each of the plurality of address qubits is represented by a respective mode of the bosonic system;

initialize a plurality of register qubits, wherein each of the plurality of register qubits is represented by a respective mode of the bosonic system; and

perform a plurality of quantum gates by providing energy to the superconducting circuit, each quantum gate changing a state of at least one of the plurality of register qubits based at least in part on a state of one of the plurality of address qubits.

19 . The QRAM system of claim 18 , wherein performing each quantum gate of the plurality of quantum gates comprises driving the superconducting circuit with two drives of different frequencies selected based on frequencies of modes of the bosonic system.

20 . The QRAM system of claim 12 , wherein the memory is a quantum memory storing a plurality of qubits.

21 . The QRAM system of claim 12 , wherein the memory is a classical memory storing a plurality of bits.

Assignments (1)

Continuity (2)

References Cited (32)