IP Library Granted Patent US 11,798,474
Granted Patent B2
US 11,798,474 · App. 17/435,249 · Granted Oct 24, 2023

Display panel, driving method thereof and display device

Inventors: Li Wang (Beijing, CN); Qian Yang (Beijing, CN); Tian Dong (Beijing, CN); Renrong Gai (Beijing, CN); Jingquan Wang (Beijing, CN); Bo Wang (Beijing, CN)
Assignee: BOE Technology Group Co., Ltd.
G09G3/3233H10K59/131G09G2300/0842G09G2310/061G09G2310/08G09G2320/0214G09G2320/0247
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Quick Facts
Patent No.
US 11,798,474
App. No.
17/435,249
Granted
Oct 24, 2023
Kind
B2
Abstract

A display panel and a driving method thereof and a display device are provided. The display panel includes a pixel circuit and a light-emitting element, the pixel circuit including a driving transistor, a first reset transistor and a second reset transistor; the first reset transistor being connected with a gate electrode of the driving transistor and configured to reset the gate electrode of the driving transistor, and the second reset transistor being configured to reset the first electrode of the light-emitting element; a first initialization signal line, connected with the gate electrode of the driving transistor through the first reset transistor; and a second initialization signal line, connected with the first electrode of the light-emitting element through the second reset transistor. The first initialization signal line and the second initialization signal line are insulated from each other and are configured to supply signals respectively.

Claims (45)

1. A display panel, comprising:

a light-emitting unit, comprising a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the pixel circuit comprising a driving transistor, a first reset transistor and a second reset transistor; the first reset transistor being connected with a gate electrode of the driving transistor and configured to reset the gate electrode of the driving transistor, and the second reset transistor being connected with a first electrode of the light-emitting element and being configured to reset the first electrode of the light-emitting element;

a first initialization signal line, connected with the gate electrode of the driving transistor through the first reset transistor; and

a second initialization signal line, connected with the first electrode of the light-emitting element through the second reset transistor,

wherein the first initialization signal line and the second initialization signal line are insulated from each other and are configured to supply signals respectively;

the first reset transistor is a dual-gate transistor, the first reset transistor comprises a first channel and a second channel, and the first channel and the second channel are connected by a first conductive connection portion;

the display panel further comprises a base substrate and a first power line which is configured to supply a first voltage signal to the pixel circuit; and

an orthographic projection of the first conductive connection portion on the base substrate is completely within an orthographic projection of the first power line on the base substrate.

2. The display panel according to claim 1 , wherein a first electrode of the first reset transistor is connected with the first initialization signal line, and a second electrode of the first reset transistor is connected with the gate electrode of the driving transistor;

a first electrode of the second reset transistor is connected with the second initialization signal line, and a second electrode of the second reset transistor is connected with the first electrode of the light-emitting element.

3. The display panel according to claim 1 , wherein the first initialization signal line is configured to supply an alternating current signal;

the first initialization signal line is configured to supply a first voltage to the first reset transistor in a phase of resetting the gate electrode of the driving transistor and configured to supply a second voltage to the first reset transistor in a light-emitting phase of the light-emitting element, and the second voltage is greater than the first voltage.

4. The display panel according to claim 1 , wherein the second initialization signal line is configured to supply a direct current signal.

5. The display panel according to claim 1 , wherein the first initialization signal line and the second initialization signal line are both extended in a first direction, and the light-emitting unit comprises a first light-emitting unit and a second light-emitting unit that are adjacent to each other in a second direction, the second direction intersecting with the first direction;

in the second direction, the second initialization signal line of the second light-emitting unit and the first initialization signal line of the first light-emitting unit are located between the driving transistor of the first light-emitting unit and the driving transistor of the second light-emitting unit; and

the second initialization signal line of the second light-emitting unit is closer to the driving transistor of the first light-emitting unit than the first initialization signal line of the first light-emitting unit.

6. The display panel according to claim 5 , wherein

an orthographic projection of the first conductive connection portion of the first reset transistor of the first light-emitting unit on the base substrate at least partially falls within an orthographic projection of the second initialization signal line of the second light-emitting unit on the base substrate.

7. The display panel according to claim 6 , further comprising a reset control signal line,

wherein a first gate electrode and a second gate electrode of the first reset transistor are parts of the reset control signal line, respectively.

8. The display panel according to claim 6 ,

wherein

the pixel circuit further comprises a storage capacitor, a first electrode of the storage capacitor is connected with the gate electrode of the driving transistor, and a second electrode of the storage capacitor is connected with the first power line.

9. The display panel according to claim 8 , wherein the gate electrode of the driving transistor is connected with a second electrode of the first reset transistor through a connecting line, and an orthographic projection of the first power line on the base substrate at least partially overlap with an orthographic projection of the connecting line on the base substrate.

10. The display panel according to claim 8 , further comprising a power connection line, wherein the first power line is connected with the second electrode of the storage capacitor through the power connection line.

11. The display panel according to claim 10 , further comprising a connection electrode,

wherein one end of the connection electrode is electrically connected with the first initialization signal line, and the other end of the connection electrode is electrically connected with a first electrode of the first reset transistor;

a plurality of connection electrodes and a plurality of power connection lines are provided, and the plurality of connection electrodes and the plurality of power connection lines are alternately arranged in the second direction.

12. The display panel according to claim 8 , further comprising a gate line and a data line,

wherein the gate line is configured to input a scan signal to the pixel circuit, and the data line is configured to input a data signal to the pixel circuit; and

the pixel circuit further comprises a data writing transistor, a gate electrode of the data writing transistor is connected with the gate line, a first electrode of the data writing transistor is connected with the data line, and a second electrode of the driving transistor is connected with a first electrode of the driving transistor.

13. The display panel according to claim 12 , wherein the pixel circuit further comprises a threshold compensation transistor, a gate electrode of the threshold compensation transistor is connected with the gate line, and a first electrode of the threshold compensation transistor is connected with a second electrode of the driving transistor, and a second electrode of the threshold compensation transistor is connected with the gate electrode of the driving transistor.

14. The display panel according to claim 8 , further comprising a light-emitting control signal line,

wherein the pixel circuit further comprises a first light-emitting control transistor and a second light-emitting control transistor,

a gate electrode of the first light-emitting control transistor is connected with the light-emitting control signal line, a first electrode of the first light-emitting control transistor is connected with the first power line, and a second electrode of the first light-emitting control transistor is connected with a first electrode of the driving transistor;

a gate electrode of the second light-emitting control transistor is connected with the light-emitting control signal line, a first electrode of the second light-emitting control transistor is connected with a second electrode of the driving transistor, and a second electrode of the second light-emitting control transistor is connected with the first electrode of the light-emitting element.

15. The display panel according to claim 1 , wherein orthographic projections of a first gate electrode and a second gate electrode of the first reset transistor on the base substrate are respectively overlapped with orthographic projections of the first channel and the second channel of the first reset transistor on the base substrate.

16. The display panel according to claim 1 , wherein the first power line is in a grid shape and comprises a first portion extended in the first direction and a second portion extended in the second direction, and the first portion intersects with the second portion; and

the first portion and the second portion are in a same layer and connected in an integral structure.

17. The display panel according to claim 16 , wherein the threshold compensation transistor is a dual-gate transistor, the threshold compensation transistor comprises a first channel and a second channel, and the first channel and the second channel of the threshold compensation transistor are connected by a second conductive connection portion, and an orthographic projection of the second conductive connection portion on the base substrate is at least partially overlapped with the orthographic projection of the first power line on the base substrate.

18. The display panel according to claim 17 , further comprising a blocking portion, wherein the blocking portion is connected with the first power line, an orthographic projection of the second conductive connection portion on the base substrate is at least partially overlapped with an orthographic projection of the blocking portion on the base substrate, and the blocking portion and the second conductive connection portion form a stabilization capacitor.

19. A display device comprising the display panel according to claim 1 .

20. A driving method of the display panel according to claim 1 , comprising:

in a reset phase, resetting the gate electrode of the driving transistor and resetting the first electrode of the light-emitting element; resetting the gate electrode of the driving transistor comprising: setting a reset control signal to be a turn-on voltage, and turning on a first reset transistor, supplying a first voltage to the first electrode of the first reset transistor to transmit the first voltage to the gate electrode of the driving transistor through the first reset transistor, a second electrode being connected with the gate electrode of the driving transistor, a gate electrode of the first reset transistor being connected with a reset control signal line, and the reset control signal line being configured to supply the reset control signal;

in a light-emitting phase, driving the light-emitting element to emit light, and supplying a second voltage to the first electrode of the first reset transistor, the second voltage being greater than the first voltage.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2021
From: WANG, LI; YANG, QIAN; DONG, TIAN; GAI, RENRONG; WANG, JINGQUAN; WANG, BO
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 057389/0406 →
Continuity (1)
Related Publication 20220215799A1 · Jul 7, 2022