IP Library › Granted Patent US 11,727,873
Granted Patent B2
US 11,727,873 · App. 17/440,811 · Granted Aug 15, 2023

Semiconductor device and method for operating semiconductor device

Inventors: Kiyotaka Kimura (Isehara, JP); Hidetomo Kobayashi (Isehara, JP); Takayuki Ikeda (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G09G3/3233H01L27/1225G09G3/3275G09G2300/0465G09G2310/0291G09G2320/0252G09G2320/041G09G2330/021H10K59/12
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Quick Facts
Patent No.
US 11,727,873
App. No.
17/440,811
Granted
Aug 15, 2023
Kind
B2
Abstract

A semiconductor device with low power consumption is provided. A semiconductor device that operates at high speed is provided. A semiconductor device with a small circuit area is provided. A novel semiconductor device is provided. In the semiconductor device, a signal line is electrically connected to a plurality of pixels between a first node and a second node; an amplifier circuit has a function of amplifying a supplied current and supplying the amplified current to the first node; an analog-to-digital converter circuit has a function of converting a potential of the first node into a first signal, and a function of converting a potential of the second node into a second signal; a sensing circuit has a function of comparing the first signal and the second signal and generating a third signal; and the current amplification factor of the amplifier circuit is determined in accordance with the third signal.

Claims (26)

1. A semiconductor device comprising:

a signal line comprising a first node and a second node;

a plurality of pixels electrically connected to the signal line and positioned between the first node and the second node;

an analog-to-digital converter circuit electrically connected to the first node and the second node;

a sensing circuit electrically connected to the analog-to-digital converter circuit; and

an amplifier circuit electrically connected to the first node and supplied with an image signal,

wherein the analog-to-digital converter circuit is configured to convert a potential of the first node into a first signal, and to convert a potential of the second node into a second signal,

wherein the sensing circuit is configured to generate a third signal by a comparison result of the first signal and the second signal, and

wherein the amplifier circuit is configured to amplify the image signal in accordance with the third signal, and to output an amplified image signal to the first node.

2. The semiconductor device according to claim 1 ,

wherein each of the plurality of pixels comprises a transistor comprising a metal oxide in a channel formation region, and

wherein the metal oxide comprises an element M and Zn; where M is Al, Ga, Y, or Sn.

3. The semiconductor device according to claim 1 ,

wherein each of the plurality of pixels comprises a display element.

4. The semiconductor device according to claim 1 ,

wherein at least one of the analog-to-digital converter circuit, the sensing circuit, and the amplifier circuit comprises a transistor comprising silicon in a channel formation region.

5. The semiconductor device according to claim 1 ,

wherein at least one of the analog-to-digital converter circuit, the sensing circuit, and the amplifier circuit comprises a region overlapping with at least one of the plurality of pixels.

6. The semiconductor device according to claim 1 ,

wherein a first input terminal of the analog-to-digital converter circuit is electrically connected to the first node,

wherein a second input terminal of the analog-to-digital converter circuit is electrically connected to the second node, and

wherein an output terminal of the analog-to-digital converter circuit is electrically connected to the sensing circuit.

7. The semiconductor device according to claim 1 ,

wherein a first input terminal of the amplifier circuit is supplied with the image signal,

wherein a second input terminal of the amplifier circuit is supplied with the third signal, and

wherein an output terminal of the amplifier circuit is electrically connected to the first node.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2021
From: KIMURA, KIYOTAKA; KOBAYASHI, HIDETOMO; IKEDA, TAKAYUKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 057524/0277 →
Priority Claims (1)
JP 2019-089656 · May 10, 2019 · national
Continuity (1)
Related Publication 20220189398A1 · Jun 16, 2022