High power module package structures

1. A method, comprising:

disposing a semiconductor die and a conductive spacer between a first high voltage isolation carrier and a second high voltage isolation carrier, the semiconductor die being thermally coupled to the conductive spacer, the semiconductor die being electrically coupled to the first high voltage isolation carrier by a coupling layer;

disposing a first molding material in contact with the coupling layer in a space between the semiconductor die and the first high voltage isolation carrier, the first molding material being an electrically isolating material; and

encapsulating the first molding material and the conductive spacer with a second molding material, the second molding material being an electrically isolating material.

2. The method of claim 1 , further comprising:

coupling the semiconductor die to the first high voltage isolation carrier in a flip chip configuration using at least one of a solder bump, a preform solder, a solder paste, sintering or a fusion bond.

3. The method of claim 1 , wherein a surface of the conductive spacer includes a circumferential groove and the semiconductor die is coupled to the surface of conductive spacer within the circumferential groove.

4. The method of claim 1 , wherein the conductive spacer has a rectangular shape with rounded corners.

5. The method of claim 1 , wherein the semiconductor die has a rectangular shape with rounded corners.

6. The method of claim 1 , wherein at least one of the first high voltage isolation carrier or the second high voltage isolation carrier is a direct bonded metal (DBM) substrate.

7. The method of claim 1 , wherein at least one of the first molding material or the second molding material is an encapsulation material.

8. The method of claim 1 , wherein the conductive spacer is an electrically and thermally conductive spacer.

9. A method, comprising:

disposing a first semiconductor die between a first direct bonded metal (DBM) substrate and a second DBM substrate, the first semiconductor die being thermally coupled to the first DBM substrate; and

disposing a first conductive spacer between the first semiconductor die and the second DBM substrate, the first conductive spacer being thermally coupled to the first semiconductor die and being thermally coupled to the second DBM substrate by a coupling layer, the coupling layer being at least one of a solder, a solder bump, a preform solder, a solder paste, a sinter or a fusion bond;

disposing a first molding material in a space between the first semiconductor die and the first DBM substrate; and

disposing a second molding material encapsulating the first molding material and the first conductive spacer.

10. The method of claim 9 , further comprising:

disposing a supporting pillar extending from the first DBM substrate to the second DBM substrate.

11. The method of claim 9 , wherein the first molding material disposed in the space between the first DBM substrate is thermally coupled to the first DBM substrate, and the second molding material encapsulating the first molding material and the first semiconductor die is thermally coupled to the second DBM substrate.

12. The method of claim 9 , wherein the first semiconductor die includes at least one insulated-gate bipolar transistor device or at least one fast recovery diode.

13. The method of claim 9 , further comprising:

disposing a second semiconductor die and a second conductive spacer between the first DBM substrate and the second DBM substrate, the second semiconductor die being thermally coupled to the second conductive spacer, a first of the second semiconductor die or the second conductive spacer being thermally coupled to the first DBM substrate and a second of the second semiconductor die and the second conductive spacer being thermally coupled to the second DBM substrate.

14. A method comprising:

disposing a first semiconductor die between a first direct bonded metal (DBM) substrate and a second DBM substrate, the first semiconductor die being thermally coupled to the first DBM substrate in a flip chip configuration using at least one of a solder bump, a preform solder, a solder paste, sintering or a fusion bond;

disposing a first conductive spacer between first semiconductor die and the second DBM substrate, the first conductive spacer being thermally coupled to first semiconductor die and to the second DBM substrate;

disposing a first molding material in a gap between the first semiconductor die in the flip chip configuration and the first DBM substrate; and

disposing a second semiconductor die and a second conductive spacer between the first DBM substrate and the second DBM substrate, the second semiconductor die being thermally coupled to the second conductive spacer,

a first of the second semiconductor die or the second conductive spacer being thermally coupled to the first DBM substrate and a second of the second semiconductor die and the second conductive spacer being thermally coupled to the second DBM substrate.

15. The method of claim 14 further comprising:

disposing a supporting pillar extending from the first DBM substrate to the second DBM substrate.

16. The method of claim 14 , wherein the disposing a first semiconductor die includes disposing at least one insulated-gate bipolar transistor device and the disposing the second semiconductor die includes disposing at least one fast recovery diode.

17. The method of claim 14 further comprising:

coupling the second conductive spacer to the second semiconductor die.

18. The method of claim 14 further comprising:

coupling the second conductive spacer to the first DBM substrate.