IP Library Granted Patent US 11,796,888
Granted Patent B2
US 11,796,888 · App. 17/443,420 · Granted Oct 24, 2023

Method and system for a vertical junction high-speed phase modulator

Inventors: Attila Mekis (Carlsbad, CA); Subal Sahni (La Jolla, CA); Yannick De Koninck (Mechelen, BE); Gianlorenzo Masini (Carlsbad, CA); Faezeh Gholami (Guttenberg, NJ)
Assignee: Cisco Technology, Inc.
G02F1/2257G02F1/025G02F1/212G02F2201/063G02F2201/12
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Quick Facts
Patent No.
US 11,796,888
App. No.
17/443,420
Granted
Oct 24, 2023
Kind
B2
Abstract

Methods and systems for a vertical junction high-speed phase modulator are disclosed and may include a semiconductor device having a semiconductor waveguide including a slab section, a rib section extending above the slab section, and raised ridges extending above the slab section on both sides of the rib section. The semiconductor device has a vertical pn junction with p-doped material and n-doped material arranged vertically with respect to each other in the rib and slab sections. The rib section may be either fully n-doped or p-doped in each cross-section along the semiconductor waveguide. Electrical connection to the p-doped and n-doped material may be enabled by forming contacts on the raised ridges, and electrical connection may be provided to the rib section from one of the contacts via periodically arranged sections of the semiconductor waveguide, where a cross-section of both the rib section and the slab section in the periodically arranged sections may be fully n-doped or fully p-doped.

Claims (32)

1. A semiconductor device, the device comprising:

a semiconductor waveguide comprising a slab section, a rib section extending above the slab section, and raised ridges extending above the slab section on both sides of the rib section;

a first portion of the semiconductor waveguide with a vertical pn junction with p-doped material and n-doped material arranged vertically with respect to each other in the rib section and the slab section, respectively, wherein the rib section is either fully n-doped or fully p-doped along the semiconductor waveguide in the first portion;

a second portion of the semiconductor waveguide with a horizontal pn junction with p-doped material and n-doped material arranged laterally with respect to each other in both the rib section and the slab section, wherein a portion of the slab section in the second portion of the semiconductor waveguide is undoped; and

electrical contact to the p-doped material and n-doped material via contacts on the raised ridges.

2. The device according to claim 1 , wherein the undoped portion of the slab section is between the raised ridges and the rib section.

3. The device according to claim 1 , wherein the raised ridges are separated from the rib section by trenches.

4. The device according to claim 3 , wherein an undoped portion of the slab section is below one of the trenches.

5. The device according to claim 1 , wherein the semiconductor waveguide comprises a first phase modulation section of an optical modulator.

6. The device according to claim 1 , wherein the semiconductor waveguide comprises silicon.

7. The device according to claim 1 , wherein the semiconductor waveguide is integrated in a complementary metal-oxide semiconductor (CMOS) die.

8. A semiconductor device, the device comprising:

a semiconductor waveguide comprising a slab section, a rib section extending above the slab section, and raised ridges extending above the slab section on both sides of the rib section, wherein the raised ridges are separated from the rib section by trenches, and wherein an undoped portion of the slab section is below one of the trenches;

a first portion of the semiconductor waveguide with a vertical pn junction with p-doped material and n-doped material arranged vertically with respect to each other in the rib section and the slab section, respectively, wherein the rib section is either fully n-doped or fully p-doped along the semiconductor waveguide in the first portion;

a second portion of the semiconductor waveguide with a horizontal pn junction with p-doped material and n-doped material arranged laterally with respect to each other in both the rib section and the slab section; and

electrical contact to the p-doped material and n-doped material via contacts on the raised ridges.

9. The device according to claim 8 , wherein a portion of the slab section in the second portion of the semiconductor waveguide is undoped.

10. The device according to claim 9 , wherein the undoped portion of the slab section in the second portion of the semiconductor waveguide is between the raised ridges and the rib section.

11. The device according to claim 8 , wherein the semiconductor waveguide comprises a first phase modulation section of an optical modulator.

12. The device according to claim 8 , wherein the semiconductor waveguide comprises silicon.

13. The device according to claim 8 , wherein the semiconductor waveguide is integrated in a complementary metal-oxide semiconductor (CMOS) die.

14. A semiconductor device, the device comprising:

a semiconductor waveguide comprising a slab section, a rib section extending above the slab section, and raised ridges extending above the slab section on both sides of the rib section, wherein an undoped portion of the slab section is between the raised ridges and the rib section;

a first portion of the semiconductor waveguide with a vertical pn junction with p-doped material and n-doped material arranged vertically with respect to each other in the rib section and the slab section, respectively, wherein the rib section is either fully n-doped or fully p-doped along the semiconductor waveguide in the first portion;

a second portion of the semiconductor waveguide with a horizontal pn junction with p-doped material and n-doped material arranged laterally with respect to each other in both the rib section and the slab section; and

electrical contact to the p-doped material and n-doped material via contacts on the raised ridges.

15. The device according to claim 14 , wherein a portion of the slab section in the second portion of the semiconductor waveguide is undoped.

16. The device according to claim 14 , wherein the raised ridges are separated from the rib section by trenches.

17. The device according to claim 16 , wherein an undoped portion of the slab section is below one of the trenches.

18. The device according to claim 14 , wherein the semiconductor waveguide comprises a first phase modulation section of an optical modulator.

19. The device according to claim 14 , wherein the semiconductor waveguide comprises silicon.

20. The device according to claim 14 , wherein the semiconductor waveguide is integrated in a complementary metal-oxide semiconductor (CMOS) die.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 058979 FRAME: 0027. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 24, 2022
From: LUXTERA LLC
To: CISCO TECHNOLOGY, INC.
Reel/Frame 059496/0803 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2022
From: CISCO SYSTEMS, INC.
To: CISCO TECHNOLOGY, INC.
Reel/Frame 058979/0027 →
Continuity (4)
Continuation 16206749 · Nov 30, 2018
Division 15694236 · Sep 1, 2017
Provisional Application 62382326 · Sep 1, 2016
Related Publication 20220019121A1 · Jan 20, 2022