Back end of line embedded RRAM structure with grain growth enhancement
A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a bottom electrode and a top electrode separated by a dielectric film. A portion of the dielectric film directly above the bottom electrode may be doped and crystalline. The semiconductor structure may include a stud below and in electrical contact with the bottom electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.
1. A semiconductor structure comprising:
a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip, the resistive random access memory includes a bottom electrode and a top electrode separated by a dielectric film, wherein a portion of the dielectric film directly above the bottom electrode is doped and crystalline;
a stud below and in electrical contact with the bottom electrode and the lower metal interconnect; and
a dielectric layer between the upper metal interconnect and the lower metal interconnect, the dielectric layer separates the upper metal interconnect from the lower metal interconnect.
2. The semiconductor structure of claim 1 , wherein the crystalline portion of the dielectric film includes grain boundaries that extend through an entire thickness of the dielectric film.
3. The semiconductor structure of claim 1 , wherein the crystalline portion of the dielectric film includes grains, wherein an average grain size is larger than a thickness of the dielectric film.
4. The semiconductor structure of claim 3 , wherein the grains have non-ferroelectric properties.
5. The semiconductor structure of claim 1 , wherein the dielectric film is made of hafnium oxide.
6. The semiconductor structure of claim 1 , wherein the dopant is silicon or zirconium.
7. The semiconductor structure of claim 1 , wherein the stud bridges a distance from the bottom electrode of the resistive random access memory to the lower metal interconnect.
8. A semiconductor structure comprising:
a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip, the resistive random access memory includes a bottom electrode and a top electrode separated by a dielectric film, wherein the top electrode is below and in electrical contact with the upper metal interconnect, wherein a portion of the dielectric film directly above the bottom electrode is doped and crystalline;
a stud below and in electrical contact with the bottom electrode and the lower metal interconnect, wherein the stud is made of a refractory metal; and
a dielectric layer between the upper metal interconnect and the lower metal interconnect, the dielectric layer separates the upper metal interconnect from the lower metal interconnect.
9. The semiconductor structure of claim 8 , wherein the crystalline portion of the dielectric film includes grain boundaries that extend through an entire thickness of the dielectric film.
10. The semiconductor structure of claim 8 , wherein the crystalline portion of the dielectric film includes grains, wherein an average grain size is larger than a thickness of the dielectric film.
11. The semiconductor structure of claim 10 , wherein the grains have non-ferroelectric properties.
12. The semiconductor structure of claim 8 , wherein the dopant is silicon or zirconium.
13. The semiconductor structure of claim 8 , wherein the dielectric film is made of hafnium oxide.
14. A method comprising:
forming a stud below and in electrical contact with a bottom electrode and a lower metal interconnect;
depositing a dielectric layer between an upper metal interconnect and the lower metal interconnect, the dielectric layer separates the upper metal interconnect from the lower metal interconnect;
forming a resistive random access memory device embedded between the upper metal interconnect and the lower metal interconnect in a backend structure of a chip, the resistive random access memory includes a bottom electrode and a top electrode separated by a dielectric film;
locally doping with a dopant a portion of the dielectric film above the bottom electrode; and
annealing the dielectric film to crystalize the doped portion of the dielectric film above the bottom electrode.
15. The method of claim 14 , wherein the crystalline portion of the dielectric film includes grain boundaries that extend through an entire thickness of the dielectric film.
16. The method of claim 14 , wherein the crystalline portion of the dielectric film includes grains, wherein an average grain size is larger than a thickness of the dielectric film.
17. The method of claim 16 , wherein the grains have non-ferroelectric properties.
18. The method of claim 14 , wherein the dopant is silicon or zirconium.
19. The method of claim 14 , wherein annealing comprises laser annealing.
20. The method of claim 14 , wherein locally doping comprises ion implantation of doping atoms.