Selective dual silicide formation
Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.
1. A method, comprising:
forming a p-type source/drain region over a substrate;
forming an n-type source/drain region over the substrate;
performing, under an at least partial vacuum, a pre-clean operation to clean a top surface of the p-type source/drain region and a top surface of the n-type source/drain region;
forming a p-type metal silicide layer on the p-type source/drain region without breaking the at least partial vacuum;
forming an n-type metal silicide layer on the n-type source/drain region after forming the p-type metal silicide layer on the p-type source/drain region;
forming a first source/drain contact over the p-type metal silicide layer; and
forming a second source/drain contact over the n-type metal silicide layer.
2. The method of claim 1 , wherein forming the n-type metal silicide layer on the n-type source/drain region comprises:
forming the n-type metal silicide layer on the n-type source/drain region without breaking the at least partial vacuum after forming the p-type metal silicide layer on the p-type source/drain region.
3. The method of claim 1 , wherein the n-type metal silicide layer is selectively formed on the n-type source/drain region and without a mask over the p-type source/drain region.
4. The method of claim 1 , further comprising:
forming the n-type metal silicide layer on the p-type metal silicide layer over the p-type source/drain region,
wherein forming the first source/drain contact over the p-type metal silicide layer comprises:
forming the first source/drain contact on the n-type metal silicide layer that is on the p-type metal silicide layer.
5. The method of claim 1 , further comprising:
forming, in a same deposition operation, a metal barrier layer over the p-type metal silicide layer and over the n-type metal silicide layer prior to forming the first source/drain contact and prior to forming the second source/drain contact.
6. The method of claim 1 , wherein a thickness of the n-type metal silicide layer is greater than a thickness of the p-type metal silicide layer.
7. The method of claim 1 , wherein the p-type metal silicide layer is selectively formed on the p-type source/drain region and without a mask over the n-type source/drain region.
8. A method, comprising:
performing, in a first processing chamber and under an at least partial vacuum, a pre-clean operation to clean a top surface of a p-type source/drain region of a semiconductor device and to clean a top surface of an n-type source/drain region of the semiconductor device;
transferring, after performing the pre-clean operation, the semiconductor device to a second processing chamber while maintaining the at least partial vacuum;
forming, in the second processing chamber and under the at least partial vacuum, a p-type metal silicide layer on the top surface of the p-type source/drain region;
transferring, after forming the p-type metal silicide layer, the semiconductor device to a third processing chamber while maintaining the at least partial vacuum; and
forming, in the third processing chamber and under the at least partial vacuum, an n-type metal silicide layer on the top surface of the n-type source/drain region.
9. The method of claim 8 , further comprising:
transferring, after forming the n-type metal silicide layer, the semiconductor device to a fourth processing chamber while maintaining the at least partial vacuum; and
forming, in the fourth processing chamber and under the at least partial vacuum, a metal nitride barrier layer over the p-type metal silicide layer and over the n-type metal silicide layer.
10. The method of claim 8 , wherein forming the p-type metal silicide layer on the top surface of the p-type source/drain region comprises:
forming the p-type metal silicide layer to a thickness in a range of approximately 5 angstroms to approximately 50 angstroms.
11. The method of claim 8 , further comprising:
forming the n-type metal silicide layer on the p-type metal silicide layer,
wherein a combined thickness of the n-type metal silicide layer and the p-type metal silicide layer is in a range of approximately 25 angstroms to approximately 85 angstroms.
12. The method of claim 11 , wherein a ratio of the combined thickness to a thickness of the n-type metal silicide layer on the top surface of the n-type source/drain region is in a range of approximately 1:3 to approximately 17:7.
13. The method of claim 8 , wherein forming the n-type metal silicide layer on the top surface of the n-type source/drain region comprises:
forming the n-type metal silicide layer without an intervening pre-clean operation between forming the p-type metal silicide layer and forming the n-type metal silicide layer.
14. The method of claim 8 , wherein the p-type metal silicide layer includes at least one of:
iridium silicide (IrSi),
ruthenium silicide (RuSi),
nickel silicide (NiSi),
tungsten silicide (WSi),
platinum silicide (PtSi), or
palladium silicide (PdSi).
15. A method, comprising:
providing a flow of a ruthenium (Ru) precursor into a processing chamber,
wherein the ruthenium precursor bonds to germanium (Ge) sites of a p-type source/drain region on a substrate and resists bonding to silicon (Si) sites of an n-type source/drain region on the substrate as a result of a greater dissociation energy, of a first ligand of a plurality of ligands of the ruthenium precursor, for silicon relative to a dissociation energy of the first ligand for germanium; and
providing a flow of a reactant gas into the processing chamber,
wherein the reactant gas disassociates a second ligand of the plurality of ligands from the ruthenium precursor such that ruthenium of the ruthenium precursor remains bonded to the Ge sites, which results in formation of a ruthenium silicide (RuSi) layer on the p-type source/drain region.
16. The method of claim 15 , further comprising:
providing a flow of a halogen gas into another processing chamber,
wherein the halogen gas results in passivation of the germanium sites of the p-type source/drain region; and
providing a flow of a titanium (Ti) precursor into the other processing chamber,
wherein the titanium precursor bonds to the silicon sites of the n-type source/drain region and resists bonding to the germanium sites of the p-type source/drain region as a result of the passivation of the germanium sites of the p-type source/drain region.
17. The method of claim 15 , wherein providing the flow of the ruthenium precursor and providing the flow of the reactant gas comprise:
providing the flow of the ruthenium precursor and providing the flow of the reactant gas for a plurality of alternating cycles in an atomic layer deposition (ALD) operation to form the ruthenium silicide layer on the p-type source/drain region.
18. The method of claim 17 , wherein the second ligand provides passivation of the ruthenium during the ALD operation.
19. The method of claim 15 , wherein providing the flow of the ruthenium precursor into the processing chamber comprises:
providing the flow of the ruthenium precursor into the processing chamber while a temperature inside the processing chamber is in a range of approximately 230 degrees Celsius to approximately 400 degrees Celsius.
20. The method of claim 15 , wherein the p-type source/drain region is included in a p-type metal oxide semiconductor (PMOS) region on the substrate; and
wherein the n-type source/drain region is included in an n-type metal oxide semiconductor (NMOS) region on the substrate.