Bank design with differential bulk bias in eFuse array
View Patent ↗In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first memory cell including a first resistor; and a first transistor coupled to the first resistor, wherein a first bulk port of the first transistor is biased at a first voltage level; a second memory cell coupled to the first memory cell, the second memory cell including a second resistor; and a second transistor coupled to the second memory cell, wherein a second bulk port of the second transistor is biased at a second voltage level, wherein the second voltage level is less than the first voltage level.
1. A memory circuit comprising: a first memory cell including: a first resistor; a first transistor coupled to the first resistor, wherein a first bulk port of the first transistor is biased at a first voltage level; a second memory cell coupled to the first memory cell, the second memory cell including: a second resistor; a second transistor coupled to the second memory cell, wherein a second bulk port of the second transistor is biased at a second voltage level, wherein the second voltage level is less than the first voltage level; and a read access transistor coupled to each of the first memory cell and the second memory cell, wherein, in response to the read access transistor receiving a read bit line voltage, a sensing circuit coupled to the read access transistor senses at least one of the first memory cell or the second memory cell.
2. The memory circuit of claim 1 , wherein the first transistor is a deep n-well (DNW) transistor and the second transistor is a bulk transistor.
3. The memory circuit of claim 1 , wherein each of the first transistor and the second transistor is a deep n-well (DNW) transistor.
4. The memory circuit of claim 1 , wherein the first resistor is coupled to first routing having a first resistance and the second resistor is coupled to second routing having a second resistance greater than the first resistance.
5. The memory circuit of claim 1 , wherein the first voltage level is a positive, non-zero voltage and the second voltage is zero volts.
6. The memory circuit of claim 1 , wherein each of the first voltage level and the second voltage level is a positive, non-zero voltage.
7. The memory circuit of claim 1 , wherein the first memory cell is a first electronic fuse (eFuse) and the second memory cell is a second eFuse.
8. The memory circuit of claim 1 , wherein the first eFuse is not programmed and the second eFuse is programmed.
9. The memory circuit of claim 1 , further comprising a sensing circuit coupled to the first eFuse, wherein, in response to the sensing circuit sensing the first eFuse, the first eFuse provides a signal having a voltage level of zero volts.
10. The memory circuit of claim 1 , further comprising a sensing circuit coupled to the second eFuse, wherein, in response to the sensing circuit sensing the second eFuse, the second eFuse provides a signal having a voltage level of VDD.
11. The memory circuit of claim 1 , further comprising a write access transistor coupled to each of the first memory cell and the second memory cell, wherein, in response to the write access transistor receiving a write bit line voltage, a voltage source coupled to the write access transistor programs at least one of the first memory cell or the second memory cell.
12. The memory circuit of claim 1 , wherein the second voltage level is a positive, non-zero voltage and the first voltage is zero volts.
13. The memory circuit of claim 1 , wherein each of the first voltage level and the second voltage level is a positive, non-zero voltage.
14. A memory device comprising: a substrate including a first portion and a second portion disposed over the first portion; a first bulk electrode of a first word line (WL) transistor disposed over the second portion of the substrate; a deep n-well disposed over the first portion of the substrate; a pair of n-wells disposed over the deep n-well; a p-well disposed over the deep n-well and in between the pair of n-wells; a second bulk electrode of a second word line (WL) transistor disposed over the p-well; and a read access transistor coupled to each of the first bulk electrode and the second bulk electrode, wherein, in response to the read access transistor receiving a read bit line voltage, a sensing circuit coupled to the read access transistor senses at least one of the first bulk electrode or the second bulk electrode.
15. The memory device of claim 14 , wherein the substrate includes a third portion disposed over the first portion of the substrate and opposite the p-well from the second portion of the substrate, the method memory device further comprising a third bulk electrode of the second WL transistor disposed over the third portion of the substrate.