Transistor—level defect coverage and defect simulation

1. A method comprising:

receiving an integrated circuit (IC) design;

generating, by one or more processors, a graph based on a plurality of sub-circuits of the IC design;

determining, by the one or processors, one or more candidate sub-circuits from the plurality of sub-circuits based on the graph;

identifying, by the one or more processors, one or more sub-circuits from the one or more candidate sub-circuits based on a number of transistors and a number of edges within each of the plurality of sub-circuits; and

providing an indication of the identified one or more sub-circuits.

2. The method of claim 1 , wherein identifying the one or more sub-circuits comprises:

comparing the number of transistors in each of the plurality of sub-circuits to a first threshold and a second threshold, the second threshold is greater than the first threshold; and

comparing the number of edges within each of the plurality of sub-circuits to a third threshold.

3. The method of claim 2 , wherein identifying the one or more sub-circuits comprises identifying a first sub-circuit of the plurality of sub-circuits based on a number of transistors of the first sub-circuit being greater than the first threshold and less than the second threshold, and a number of edges of the first sub-circuit being less than the third threshold.

4. The method of claim 1 , wherein generating the graph for the plurality of sub-circuits comprises:

detecting channel-connected blocks based on nodes of the plurality of sub-circuits; and

placing a directed edge between an output of a first channel-connected block of the channel-connected blocks and an input of a second channel-connected block of the channel-connected blocks.

5. The method of claim 1 further comprises:

performing direct current (DC) analysis on the identified one or more sub-circuits to determine a first defect coverage amount associated with a first plurality of nets of the IC design; and

identifying a set of sensitive nets from the first plurality of nets based on the first defect coverage amounts.

6. The method of claim 5 further comprises, based on a combined defect coverage amount of the set of sensitive nets being less than a threshold value, performing transient analysis on the sub-circuits of the IC design to determine second defect coverage amounts associated with a second plurality of nets of the IC design.

7. The method of claim 6 , wherein the set of sensitive nets is further identified from the second plurality of nets based on the second defect coverage amounts.

8. A system comprising:

a memory storing instructions; and

a processor, coupled with the memory and configured to execute the instructions, the instructions when executed cause the processor to:

receive a digital design file of an integrated circuit (IC) design;

generate a channel-connected graph based on a plurality of sub-circuits of the IC design;

determine one or more candidate sub-circuits from the plurality of sub-circuits from the channel-connected graph;

identify one or more sub-circuits from the one or more candidate sub-circuits based on a number of transistors and a number of edges within each of the plurality of sub-circuits; and

output an indication of the identified one or more sub-circuits.

9. The system of claim 8 , wherein identifying the one or more sub-circuits comprises:

comparing the number of transistors in each of the plurality of sub-circuits to a first threshold and a second threshold, the second threshold is greater than the first threshold; and

comparing the number of edges within each of the plurality of sub-circuits to a third threshold.

10. The system of claim 9 , wherein identifying the one or more sub-circuits comprises identifying a first sub-circuit of the plurality of sub-circuits based on a number of transistors the first sub-circuit being greater than the first threshold and less than the second threshold, and a number of edges of the first sub-circuit being less than the third threshold.

11. The system of claim 8 , wherein generating the channel-connected graph for the plurality of sub-circuits comprises:

detecting channel-connected blocks based on nodes of the plurality of sub-circuits; and

placing a directed edge between an output of a first channel-connected block of the channel-connected blocks and an input of a second channel-connected block of the channel-connected blocks.

12. The system of claim 8 , wherein the instructions when executed cause the processor to further:

perform direct current (DC) analysis on the identified one or more sub-circuits to determine a first defect coverage amount associated with a first plurality of nets of the IC design; and

identify a set of sensitive nets from the first plurality of nets based on the first defect coverage amounts.

13. The system of claim 12 , wherein, based on a combined defect coverage amount of the set of sensitive nets being less than a threshold value, performing transient analysis on the sub-circuits of the IC design to determine second defect coverage amounts associated with a second plurality of nets of the IC design.

14. The system of claim 13 , wherein the set of sensitive nets is further identified from the second plurality of nets based on the second defect coverage amounts.

15. A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

receive an integrated circuit (IC) design;

generate a graph for a plurality of sub-circuits of the IC design;

determine one or more candidate sub-circuits from the plurality of sub-circuits from the graph;

identify one or more sub-circuits from the one or more candidate sub-circuits based on a number of transistors and a number of edges within each of the plurality of sub-circuits; and

provide an indication of the identified one or more sub-circuits.

16. The non-transitory computer readable medium of claim 15 , wherein identifying the one or more sub-circuits comprises:

comparing the number of transistors in each of the plurality of sub-circuits to a first threshold and a second threshold, the second threshold is greater than the first threshold; and

comparing the number of edges within each of the plurality of sub-circuits to a third threshold.

17. The non-transitory computer readable medium of claim 16 , wherein identifying the one or more sub-circuits comprises identifying a first sub-circuit of the plurality of sub-circuits based on a number of transistors the first sub-circuit being greater than the first threshold and less than the second threshold, and a number of edges of the first sub-circuit being less than the third threshold.

18. The non-transitory computer readable medium of claim 15 , wherein generating the graph for the plurality of sub-circuits comprises:

detecting channel-connected blocks based on nodes of the plurality of sub-circuits; and

placing a directed edge between an output of a first channel-connected block of the channel-connected blocks and an input of a second channel-connected block of the channel-connected blocks.

19. The non-transitory computer readable medium of claim 15 , wherein the processor is further caused to:

perform direct current (DC) analysis on the identified one or more sub-circuits to determine a first defect coverage amount associated with a first plurality of nets of the IC design; and

identify a set of sensitive nets from the first plurality of nets based on the first defect coverage amounts.

20. The non-transitory computer readable medium of claim 19 , wherein, based on a combined defect coverage amount of the set of sensitive nets being less than a threshold value, performing transient analysis on the sub-circuits of the IC design to determine second defect coverage amounts associated with a second plurality of nets of the IC design.