IP Library › Granted Patent US 11,751,152
Granted Patent B2
US 11,751,152 · App. 17/451,994 · Granted Sep 5, 2023

SSB structure for NR communications

Inventors: Qingjiang Tian (San Diego, CA); Xiaoxia Zhang (San Diego, CA); Jing Sun (San Diego, CA); Zhifei Fan (San Diego, CA); Arumugam Chendamarai Kannan (San Diego, CA); Jun Ma (San Diego, CA); Tao Luo (San Diego, CA); Juan Montojo (San Diego, CA)
Assignee: QUALCOMM Incorporated
H04W56/001H04L5/0051H04L27/26025
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Quick Facts
Patent No.
US 11,751,152
App. No.
17/451,994
Granted
Sep 5, 2023
Kind
B2
Abstract

In one aspect, an extended SSB (ESSB) is provided that includes more than four symbols to facilitate UE reception of SSBs. In this aspect, the base station configures an ESSB comprising an SSB including four symbols and an initial symbol preceding the SSB. The base station transmits and the UE receives at least a portion of the ESSB. The UE processes the ESSB. Thus, higher capacity UEs can benefit from additional coding gain in the initial symbol while lower capacity UEs can switch beams to receive back-to-back ESSBs. In another aspect, a UE performs additional behaviors to receive SSBs. In this aspect, the UE receives a first SSB using a reception beam, and the UE determines to maintain the reception beam for a second SSB or to switch the reception beam during a PSS symbol of the second SSB. Thus, lower capacity UEs can also receive back-to-back SSBs.

Claims (49)

1. A method of wireless communication at a user equipment (UE), comprising:

receiving, from a base station, an extended synchronization signal block (ESSB), wherein the ESSB comprises a synchronization signal block (SSB) including four symbols and an initial symbol preceding the SSB;

processing the ESSB; and

determining that the ESSB includes more than the four symbols in response to successfully decoding the ESSB.

2. An apparatus for wireless communication, comprising:

a processor;

memory coupled with the processor; and

instructions stored in the memory and operable, when executed by the processor, to cause the apparatus to:

receive, from a base station, an extended synchronization signal block (ESSB), wherein the ESSB comprises a synchronization signal block (SSB) including four symbols and an initial symbol preceding the SSB;

process the ESSB; and

determine that the ESSB includes more than the four symbols in response to successfully decoding the ESSB.

3. The apparatus of claim 2 , wherein the initial symbol includes a physical broadcast channel (PBCH), a primary synchronization signal (PSS), or a secondary synchronization signal (SSS).

4. The apparatus of claim 2 , wherein the initial symbol is a repetition of one of the symbols of the SSB.

5. The apparatus of claim 2 , wherein a final symbol of the ESSB is adjacent to an initial symbol of a second ESSB.

6. The apparatus of claim 2 , wherein the ESSB is received in a pattern associated with a subcarrier spacing greater than 240 KHz.

7. The apparatus of claim 2 , wherein the instructions, when executed by the processor, further cause the apparatus to refrain from decoding the initial symbol of the ESSB.

8. The apparatus of claim 2 , wherein the instructions, when executed by the processor, further cause the apparatus to determine that the ESSB includes more than the four symbols in response to detecting a demodulation reference signal (DMRS) in the initial symbol of the ESSB.

9. The apparatus of claim 2 , wherein the instructions, when executed by the processor, further cause the apparatus to decode the initial symbol of the ESSB without determining the ESSB includes more than the four symbols.

10. The apparatus of claim 2 , wherein the instructions, when executed by the processor, further cause the apparatus to determine that the ESSB includes more than the four symbols based on channel estimation from a demodulation reference signal (DMRS) in the SSB.

11. The apparatus of claim 2 , wherein the instructions, when executed by the processor, further cause the apparatus to switch a reception beam during a time period for receiving the initial symbol of the ESSB.

12. The apparatus of claim 2 , wherein the instructions, when executed by the processor, further cause the apparatus to maintain a reception beam between a time for receiving the ESSB and a subsequent time for receiving a second ESSB.

13. The apparatus of claim 2 , wherein the instructions, when executed by the processor, further cause the apparatus to receive an indication of a number of the symbols of the ESSB, a time domain pattern of ESSBs, or a partial reception of the initial symbol of the ESSB.

14. The apparatus of claim 13 , wherein the indication is for the base station or another base station.

15. The apparatus of claim 13 , wherein the indication is received in dedicated signaling.

16. The apparatus of claim 13 , wherein the indication includes a quantity associated with the partial reception of the initial symbol of the ESSB.

17. The apparatus of claim 2 , wherein the base station is a standalone (SA) base station.

18. The apparatus of claim 2 , wherein the instructions, when executed by the processor, further cause the apparatus to receive an SSB indication that the ESSB includes more than the four symbols when the base station is a non-standalone (NSA) base station.

19. An apparatus for wireless communication, comprising:

a processor;

memory coupled with the processor; and

instructions stored in the memory and operable, when executed by the processor, to cause the apparatus to:

receive a first synchronization signal block (SSB) using a reception beam; and

determine to maintain the reception beam between the first SSB and for a second SSB or to switch the reception beam during a primary synchronization signal (PSS) symbol of the second SSB.

20. The apparatus of claim 19 , wherein the instructions, when executed by the processor, further cause the apparatus to refrain from decoding the second SSB.

21. The apparatus of claim 19 , wherein the instructions, when executed by the processor, further cause the apparatus to switch the reception beam during a gap between the second SSB and a third SSB.

22. The apparatus of claim 19 , wherein the instructions, when executed by the processor, further cause the apparatus to switch the reception beam during the PSS symbol.

23. The apparatus of claim 19 , wherein the instructions, when executed by the processor, further cause the apparatus to refrain from decoding the second SSB during a SSB-based radio resource management (RRM) Measurement Timing Configuration (SMTC) window.

24. An apparatus for wireless communication, comprising:

a processor;

memory coupled with the processor; and

instructions stored in the memory and operable, when executed by the processor, to cause the apparatus to:

configure an extended synchronization signal block (ESSB), wherein the ESSB comprises a synchronization signal block (SSB) including four symbols and an initial symbol preceding the SSB;

transmit to a user equipment (UE) at least a portion of the ESSB; and

transmit an SSB indication that the ESSB includes more than four symbols when the apparatus is a non-standalone (NSA) base station.

25. The apparatus of claim 24 , wherein the instructions, when executed by the processor, further cause the apparatus to:

refrain from transmitting the initial symbol of the ESSB; and

switch a transmission beam during a time period for transmitting the initial symbol.

26. The apparatus of claim 24 , wherein the instructions, when executed by the processor, further cause the apparatus to switch a transmission beam during a time period for transmitting the initial symbol of the ESSB, wherein the ESSB is transmitted during a portion of the time period after the switching.

27. The apparatus of claim 24 , wherein the instructions, when executed by the processor, further cause the apparatus to transmit an indication of a number of the symbols of the ESSB, a time domain pattern of ESSBs, or a partial transmission of the initial symbol of the ESSB.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2021
From: TIAN, QINGJIANG; ZHANG, XIAOXIA; SUN, JING; FAN, ZHIFEI; CHENDAMARAI KANNAN, ARUMUGAM; MA, JUN; LUO, TAO; MONTOJO, JUAN
To: QUALCOMM INCORPORATED
Reel/Frame 058233/0379 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2021
From: TIAN, QINGJIANG; ZHANG, XIAOXIA; SUN, JING; FAN, ZHIFEI; CHENDAMARAI KANNAN, ARUMUGAM; MA, JUN; LUO, TAO; MONTOJO, JUAN
To: QUALCOMM INCORPORATED
Reel/Frame 057882/0149 →
Continuity (2)
Provisional Application 63110894 · Nov 6, 2020
Related Publication 20220150851A1 · May 12, 2022