Method of forming merged pillar structures and method of generating layout diagram of same
A method (of generating a revised layout diagram of a conductive line structure for an IC) including: for a first set of pillar patterns that represents portions of an M(i) layer of metallization and where i is a non-negative number, the first set including first and second pillar patterns which extend in a first direction, are non-overlapping of each other with respect to the first direction, are aligned with each other and have a first distance of separation, determining a first distance of separation as between corresponding immediately adjacent members of the first set; recognizing that the first distance is less than a transverse routing (TVR) separation threshold for an M(i+j) layer of metallization, where j is an integer and j≥2; and increasing the first distance so as to become a second distance which is greater than the TVR separation threshold of the M(i+j) layer.
1. A method of forming a conductive line structure in an integrated circuit (IC), the method comprising:
forming a first set of medium pillars in a first layer of metallization (M_1st layer) and extending in a first direction, the forming a first set including:
forming a first pair of first & second medium pillars which are non-overlapping of each other relative to the first direction but which are aligned relative to the second direction perpendicular to the first direction;
forming a second pair of third & fourth medium pillars which are non-overlapping of each other relative to the first direction but which are aligned relative to a second direction, the forming the second pair including:
separating the third & fourth medium pillars from the first & second medium pillars by a first distance relative to the second direction;
forming vias correspondingly over members of the first set; and
forming a second set of short pillars in a second layer of metallization (M_2nd layer), over corresponding ones of the vias, and extending in the second direction, the M_2nd layer being over the M_1st layer; and
wherein:
members of the first set are electrically connected to corresponding members of the second set by corresponding ones of the vias; and
the first distance is greater than a minimum transverse-routing (TVR) separation threshold for the M_1st layer.
2. The method of claim 1 , wherein:
the first distance is represented by a variable S2;
a process-node by which the conductive line structure is being manufactured has a minimum end-of-line spacing, S EOL ; and
the first distance S2 has a range such that
≈(4/3)* S EOL ≤S 2≤˜2* S EOL .
3. The method of claim 1 , wherein:
a process-node by which the conductive line structure is being manufactured has a minimum length L MIN of a conductive line segment;
each of the medium pillars of the first set is an example of the conductive line segment;
each of the first to fourth medium pillars has a length L MED ; and
L MED ≈2* L MIN .
4. The method of claim 1 , wherein:
the first distance is greater than a minimum TVR separation threshold for a third layer of metallization (M_3rd layer), the M_3rd layer being over the M_2nd layer.
5. The method of claim 4 , wherein:
the first distance is greater than a minimum TVR separation threshold for a fourth layer of metallization (M_4th layer), the M_4th layer being over the M_3rd layer.
6. The method of claim 2 , wherein:
the process-node is organized according to reference tracks extending in the second direction and which are separated from each other relative to the first direction by a minimum distance T_b; and
S EOL ≈3* T _ b.
7. The method of claim 3 , wherein:
the process-node is organized according to reference tracks extending in the second direction and which are separated from each other relative to the first direction by a minimum distance T_b; and
L MIN ≈4* T _ b.
8. The method of claim 1 , wherein:
a process-node by which the conductive line structure is being manufactured has a minimum end-of-line spacing, S EOL ;
the first distance is represented by a variable S2; and
the first distance S2 is based on the minimum end-of-line spacing, S EOL .
9. The method of claim 1 , wherein:
a process-node by which the conductive line structure is being manufactured is organized according to reference tracks extending in the second direction and which are separated from each other relative to the first direction by a minimum distance T_b;
the first distance is represented by a variable S2; and
S 2 ≈7* T _ b.
10. The method of claim 1 , wherein:
relative to the second direction, the first & third medium pillars are separated by a first gap having a first size;
relative to the second direction, the second & fourth medium pillars are separated by a second gap having the first size;
the first size is represented by a variable X2A;
a process-node by which the conductive line structure is being manufactured has a minimum non-end-of-line spacing, S NEOL ; and
the first size X2A is approximately equal to minimum non-end-of-line spacing, S NEOL such that X2A≈2*S EOL .
11. The method of claim 10 , wherein:
the process-node is organized according to reference tracks extending in the first direction and which are separated from each relative to the second direction other by a minimum distance T_a;
the first size X2A is approximately equal to minimum non-end-of-line spacing, S NEOL such that X2A≈T_a.
12. A method of forming a conductive line structure in an integrated circuit (IC), the method comprising:
forming a first set of medium pillars in a first layer of metallization (M_1st layer) and extending in a first direction, the forming a first set including:
forming a first pair of first & second medium pillars which are separated from each other relative to the first direction but which are aligned relative to the second direction perpendicular to the first direction;
forming a second pair of third & fourth medium pillars which are separated from each other relative to the first direction but which are aligned relative to a second direction, the forming the second pair including:
separating the third & fourth medium pillars from the first & second medium pillars by a first distance relative to the second direction;
forming vias correspondingly over members of the first set; and
forming a second set of short pillars in a second layer of metallization (M_2nd layer), over corresponding ones of the vias, and extending in the second direction, the M_2nd layer being over the M_1st layer; and
wherein:
members of the first set are electrically connected to corresponding members of the second set by corresponding ones of the vias; and
a process-node by which the conductive line structure is being manufactured has a minimum end-of-line spacing, S EOL ;
the first distance is represented by a variable S2;
the first distance S2 is based on the minimum end-of-line spacing, S EOL ; and
the first distance is greater than a minimum transverse-routing (TVR) separation threshold for the M_1st layer.
13. The method of claim 12 , wherein:
the process-node has a minimum end-of-line spacing, S EOL ; and
the first distance S2 has a range such that
≈(4/3)* S EOL ≤S 2≤≈2* S EOL .
14. The method of claim 13 , wherein:
the process-node is organized according to reference tracks extending in the second direction and which are separated from each other relative to the first direction by a minimum distance T_b; and
S EOL ≈3* T _ b.
15. The method of claim 12 , wherein:
the first distance is greater than a minimum TVR separation threshold for a third layer of metallization (M_3rd layer), the M_3rd layer being over the M_2nd layer.
16. The method of claim 15 , wherein:
the first distance is greater than a minimum TVR separation threshold for a fourth layer of metallization (M_4th layer), the M_4th layer being over the M_3rd layer.
17. A method of forming a conductive line structure in an integrated circuit (IC), the method comprising:
forming a first set of medium pillars in a first layer of metallization (M_1st layer) and extending in a first direction, the forming a first set including:
forming a first pair of first & second medium pillars which are separated from each other relative to the first direction but which are aligned relative to the second direction perpendicular to the first direction;
forming a second pair of third & fourth medium pillars which are separated from each other relative to the first direction but which are aligned relative to a second direction, the forming the second pair including:
separating the third & fourth medium pillars from the first & second medium pillars by a first distance relative to the second direction;
forming vias correspondingly over members of the first set; and
forming a second set of short pillars in a second layer of metallization (M_2nd layer), over corresponding ones of the vias, and extending in the second direction, the M_2nd layer being over the M_1st layer; and
wherein:
members of the first set are electrically connected to corresponding members of the second set by corresponding ones of the vias; and
the first distance is greater than a minimum transverse-routing (TVR) separation threshold for the M_1st layer;
a process-node by which the conductive line structure is being manufactured has a minimum length L MIN of a conductive line segment;
each of the medium pillars of the first set is an example of the conductive line segment;
each of the first to fourth medium pillars has a length L MED ; and
L MED ≈2* L MIN .
18. The method of claim 17 , wherein:
the process-node is organized according to reference tracks extending in the second direction and which are separated from each other relative to the first direction by a minimum distance T_b; and
L MIN ≈4* T _ b.
19. The method of claim 17 , wherein:
the first distance is greater than a minimum TVR separation threshold for a third layer of metallization (M_3rd layer), the M_3rd layer being over the M_2nd layer.
20. The method of claim 19 , wherein:
the first distance is greater than a minimum TVR separation threshold for a fourth layer of metallization (M_4th layer), the M_4th layer being over the M_3rd layer.