IP Library Granted Patent US 11,757,550
Granted Patent B2
US 11,757,550 · App. 17/452,661 · Granted Sep 12, 2023

Ethernet interface and related systems, methods and devices

Inventors: Venkatraman Iyer (Austin, TX); Dixon Chen (Guangdong, CN); John Junling Zang (Guangdong, CN); Shivanand I. Akkihal (Austin, TX)
Assignee: Microchip Technology Incorporated
H04J3/062
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Quick Facts
Patent No.
US 11,757,550
App. No.
17/452,661
Granted
Sep 12, 2023
Kind
B2
Abstract

Described is a digital interface and related systems, method and devices. In some embodiments, an interface may be an interface between a link layer and a physical transmission medium. The interface may be configured for a bit rate and/or reference clock that limits electromagnetic emissions (EME), for example, as compared to a bit rate and/or clock rate specified by interfaces widely used in industry.

Claims (28)

1. A method, comprising:

clocking, using a first clock, a datapath of an Ethernet physical layer at a first clock rate; and

clocking, using a second clock generated based on the first clock, a first interface for operatively coupling the Ethernet physical layer with an Ethernet link layer, wherein clocking the first interface comprises clocking the first interface at a second clock rate that is substantially equal to a bit rate of the first interface.

2. The method of claim 1 , further comprising generating the first clock via a crystal oscillator.

3. The method of claim 1 , further comprising generating a divided clock responsive to the first clock.

4. The method of claim 3 , wherein clocking the first interface at the second clock rate that is substantially equal to a bit rate of the first interface comprises clocking, using the divided clock, the first interface at the second clock rate.

5. The method of claim 1 , wherein the second clock rate is either substantially 5 megahertz or substantially 2.5 megahertz and the first clock rate is substantially 25 megahertz.

6. The method of claim 1 , wherein clocking using the second clock comprises clocking using the second clock that has a frequency that is associated with lower electromagnetic emissions (EME) than a frequency of the first clock.

7. The method of claim 1 , further comprising crossing over from a first clock domain to a second clock domain at the datapath, wherein the first clock domain is associated with the first clock rate and the second clock domain is associated with the second clock rate.

8. The method of claim 1 , further comprising choosing the second clock rate of the first interface responsive to an electromagnetic emissions (EME) limit.

9. A system, comprising:

a datapath of an Ethernet physical layer, the datapath configured for a first clock rate; and

a first interface for operatively coupling the Ethernet physical layer to an Ethernet link layer, the first interface configured for a second clock rate that is substantially equal to a bit rate of the first interface.

10. The system of claim 9 , wherein the datapath comprises a clock and data recovery circuitry.

11. The system of claim 9 , further comprising a clocking interface configured to provide a divided clock responsive to a clock corresponding to the first clock rate.

12. The system of claim 11 , wherein the datapath is configured to cross over from a first clock domain to a second clock domain responsive to one or more control signals received from the clocking interface.

13. The system of claim 12 , wherein the first clock domain is associated with the first clock rate and the second clock domain is associated with the second clock rate.

14. The system of claim 12 , wherein the first clock domain comprises a physical medium attachment (PMA) sublayer and a physical coding (PC) sublayer, and the second clock domain comprises the first interface and a harmonizing sublayer.

15. The system of claim 9 , wherein the second clock rate is either substantially 5 megahertz or substantially 2.5 megahertz and the first clock rate is substantially 25 megahertz.

16. The system of claim 9 , wherein the first interface comprises one or more outputs, and an output of the one or more outputs is assigned to a signal for non-exclusive collision avoidance signaling.

17. A method, comprising:

clocking a datapath of an Ethernet physical layer at a first clock rate; and

clocking a first interface at a second clock rate that is substantially equal to a bit rate of the first interface, the first interface for operatively coupling the Ethernet physical layer with an Ethernet link layer.

18. The method of claim 17 , further comprising:

generating a first clock having the first clock rate; and

generating, responsive to the first clock, a second clock having the second clock rate.

19. The method of claim 18 , further comprising selecting a frequency of the second clock responsive to an electromagnetic emissions (EME) limit.

20. The method of claim 18 , further comprising providing information about the second clock to the datapath.

Assignments (1)
CORRECTIVE ASSIGNMENT TO CORRECT THE SPELLING OF FIRST INVENTORS NAME PREVIOUSLY RECORDED AT REEL: 0512227 FRAME: 0297. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 22, 2023
From: IYER, VENKATRAMAN; CHEN, DIXON; ZANG, JOHN JUNLING; AKKIHAL, SHIVANAND I.
To: MICROCHIP TECHNOLOGY INCORORATED
Reel/Frame 062835/0497 →
Priority Claims (1)
CN 201910784382.4 · Aug 23, 2019 · national
Continuity (2)
Continuation 16684419 · Nov 14, 2019
Related Publication 20220052775A1 · Feb 17, 2022