IP Library Granted Patent US 11,652,088
Granted Patent B2
US 11,652,088 · App. 17/452,824 · Granted May 16, 2023

Semiconductor device and method of forming embedded die substrate, and system-in-package modules with the same

Inventors: DeokKyung Yang (Incheon Si, KR); HunTeak Lee (Gyeongi-do, KR); SungSoo Kim (Seoul, KR); HeeSoo Lee (Kyunggi-do, KR)
Assignee: STATS ChipPAC Pte. Ltd.
H01L25/0657H01L23/538H01L23/552H01L24/11H01L24/17H01L25/0652H01L25/105H01L25/16H01L25/50H01L21/561H01L23/3128H01L24/05H01L24/13H01L24/16H01L2224/0345H01L2224/03452H01L2224/03462H01L2224/03464H01L2224/0401H01L2224/1132H01L2224/1134H01L2224/11334H01L2224/11462H01L2224/11464H01L2224/11849H01L2224/16227H01L2224/81191H01L2224/94H01L2224/97H01L2225/06517H01L2225/06572H01L2225/1023H01L2225/1041H01L2225/1058H01L2924/15311H01L2924/19105H01L2924/19106H01L2924/3025
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Quick Facts
Patent No.
US 11,652,088
App. No.
17/452,824
Granted
May 16, 2023
Kind
B2
Abstract

A semiconductor device has a first substrate. A first semiconductor component is disposed on a first surface of the first substrate. A second substrate includes a vertical interconnect structure on a first surface of the second substrate. A second semiconductor component is disposed on the first surface of the second substrate. The first semiconductor component or second semiconductor component is a semiconductor package. The first substrate is disposed over the second substrate with the first semiconductor component and second semiconductor component between the first substrate and second substrate. A first encapsulant is deposited between the first substrate and second substrate. A SiP submodule is disposed over the first substrate or second substrate opposite the encapsulant. A shielding layer is formed over the SiP submodule.

Claims (49)

1. A method of making a semiconductor device, comprising:

providing a first substrate with a first semiconductor component mounted to the first substrate;

disposing a second substrate over the first substrate with a second semiconductor component mounted to the second substrate;

depositing a first encapsulant between the first substrate and second substrate over the first semiconductor component and second semiconductor component;

disposing a vertical interconnect structure over the first substrate opposite the first encapsulant;

depositing a second encapsulant over the first substrate and vertical interconnect structure; and

forming a groove in the second encapsulant around the vertical interconnect structure.

2. The method of claim 1 , further including disposing a second vertical interconnect structure between the first substrate and second substrate.

3. The method of claim 1 , further including disposing a third semiconductor component over the first substrate in the second encapsulant.

4. The method of claim 1 , further including disposing a SiP submodule over the second substrate opposite the second semiconductor component.

5. The method of claim 1 , further including disposing a solder bump in the groove.

6. The method of claim 1 , wherein the first semiconductor component includes a shielding layer.

7. A method of making a semiconductor device, comprising:

providing a first substrate and second substrate;

disposing a first semiconductor component between the first substrate and second substrate;

depositing a first encapsulant between the first substrate and second substrate; and

depositing a second encapsulant over the first substrate with the first substrate disposed between the first encapsulant and second encapsulant.

8. The method of claim 7 , further including disposing a vertical interconnect structure between the first substrate and second substrate.

9. The method of claim 7 , further including disposing a second semiconductor component over the first substrate in the second encapsulant.

10. The method of claim 7 , further including disposing a SiP submodule over the second substrate opposite the first semiconductor component.

11. The method of claim 7 , further including disposing a vertical interconnect structure in the second encapsulant.

12. The method of claim 11 , further including forming a groove in the second encapsulant around the vertical interconnect structure.

13. The method of claim 7 , wherein the first semiconductor component includes a shielding layer.

14. A method of making a semiconductor device, comprising:

providing a first substrate;

providing a second substrate;

disposing a first semiconductor component between the first substrate and second substrate;

depositing a first encapsulant between the first substrate and second substrate;

disposing a SiP submodule over the first substrate opposite the first encapsulant; and

disposing a second encapsulant over the second substrate opposite the first encapsulant.

15. The method of claim 14 , further including disposing a vertical interconnect structure between the first substrate and second substrate.

16. The method of claim 14 , further including disposing a second semiconductor component over the second substrate opposite the first encapsulant.

17. The method of claim 14 , further including:

disposing a vertical interconnect structure over the second substrate; and

depositing the second encapsulant over the vertical interconnect structure.

18. The method of claim 14 , wherein the first semiconductor component includes a shielding layer.

19. A method of making a semiconductor device, comprising:

providing a first substrate;

providing a second substrate;

disposing a first semiconductor component between the first substrate and second substrate;

depositing a first encapsulant between the first substrate and second substrate; and

depositing a second encapsulant over the first substrate.

20. The method of claim 19 , further including disposing a vertical interconnect structure between the first substrate and second substrate.

21. The method of claim 19 , further including:

disposing a second semiconductor component over the first substrate opposite the first semiconductor component; and

depositing the second encapsulant over the second semiconductor component.

22. The method of claim 19 , further including disposing a SiP submodule over the second substrate opposite the first semiconductor component.

23. The method of claim 22 , wherein the SiP submodule includes a vertical interconnect structure.

24. The method of claim 19 , wherein the first semiconductor component includes a shielding layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2021
From: YANG, DEOKKYUNG; LEE, HUNTEAK; KIM, SUNGSOO; LEE, HEESOO
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 057960/0290 →
Continuity (3)
Continuation 16570165 · Sep 13, 2019
Division 15706584 · Sep 15, 2017
Related Publication 20220052025A1 · Feb 17, 2022