Phase detectors with alignment to phase information lost in decimation
Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.
1. A digital phase-locked loop (DPLL) comprising:
a phase detector configured to receive a reference clock signal having a first sequence of timing events and a feedback clock signal having a second sequence of timing events, the phase detector further configured to output a phase detection signal; and
a feedback divider configured to decimate the second sequence of timing events prior to the phase detector,
wherein the phase detector comprises at least one interpolation circuit configured to generate a plurality of interpolated timing events based on at least one of the first sequence of timing events or the second sequence of timing events, wherein the phase detector is further configured to generate the phase detection signal based on the plurality of interpolated timing events.
2. The DPLL of claim 1 wherein the at least one interpolation circuit approximates one or more timing events decimated by the feedback divider.
3. The DPLL of claim 1 further comprising a feedback time to digital converter (TDC) connected in a feedback loop with the feedback divider and the phase detector, wherein the feedback TDC outputs the feedback clock signal.
4. The DPLL of claim 3 further comprising a controllable oscillator in the feedback loop.
5. The DPLL of claim 1 further comprising a reference TDC configured to output the reference clock signal.
6. The DPLL of claim 1 wherein the at least one interpolation circuit generates the plurality of interpolated timing events based on a phase error indicated by the phase detection signal.
7. The DPLL of claim 1 wherein the at least one interpolation circuit generates the plurality of interpolated timing events based on interpolating a plurality of digital time stamps.
8. A digital phase-locked loop (DPLL) comprising:
a phase detector configured to receive a reference clock signal having a first sequence of timing events and a feedback clock signal having a second sequence of timing events, the phase detector further configured to output a phase detection signal; and
a reference divider configured to decimate the first sequence of timing events prior to the phase detector,
wherein the phase detector comprises at least one interpolation circuit configured to generate a plurality of interpolated timing events based on at least one of the first sequence of timing events or the second sequence of timing events, wherein the phase detector is further configured to generate the phase detection signal based on the plurality of interpolated timing events.
9. The DPLL of claim 8 wherein the at least one interpolation circuit approximates one or more timing events decimated by the reference divider.
10. The DPLL of claim 8 further comprising a feedback divider configured to decimate the second sequence of timing events prior to the phase detector.
11. A method of phase detection, the method comprising:
receiving a reference clock signal having a first sequence of timing events as a first input to a phase detector of a digital phase-locked loop (DPLL);
receiving a feedback clock signal having a second sequence of timing events as a second input to the phase detector;
decimating the second sequence of timing events using a feedback divider;
generating a plurality of interpolated timing events based on at least one of the first sequence of timing events or the second sequence of timing events using at least one interpolation circuit of the phase detector; and
outputting a phase detection signal from the phase detector, including generating the phase detection signal based on the plurality of interpolated timing events.
12. The method of claim 11 further comprising outputting the feedback clock signal from a feedback time to digital converter (TDC) that is connected in a feedback loop with the feedback divider and the phase detector.
13. The method of claim 12 further comprising providing feedback using a controllable oscillator in the feedback loop.
14. The method of claim 11 further comprising outputting the reference clock signal from a reference TDC.
15. The method of claim 11 further comprising generating the plurality of interpolated timing events based on a phase error indicated by the phase detection signal.
16. The method of claim 11 further comprising generating the plurality of interpolated timing events based on interpolating a plurality of digital time stamps.
17. A method of phase detection, the method comprising:
receiving a reference clock signal having a first sequence of timing events as a first input to a phase detector of a digital phase-locked loop (DPLL);
receiving a feedback clock signal having a second sequence of timing events as a second input to the phase detector;
decimating the first sequence of timing events using a reference divider;
generating a plurality of interpolated timing events based on at least one of the first sequence of timing events or the second sequence of timing events using at least one interpolation circuit of the phase detector; and
outputting a phase detection signal from the phase detector, including generating the phase detection signal based on the plurality of interpolated timing events.
18. The method of claim 17 further comprising approximating one or more timing events decimated by the reference divider using the at least one interpolation circuit.
19. The method of claim 17 further comprising decimating the second sequence of timing events using a feedback divider.
20. The method of claim 19 further comprising approximating one or more timing events decimated by the feedback divider using the at least one interpolation circuit.