IP Library › Granted Patent US 12,166,079
Granted Patent B2
US 12,166,079 · App. 17/455,146 · Granted Dec 10, 2024

2D channel transistors with low contact resistance

Inventors: Mrunal Abhijith Khaderbad (Hsinchu, TW); Dhanyakumar Mahaveer Sathaiya (Hsinchu, TW); Wei-Yen Woon (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L29/1054H01L29/24H01L29/401H01L29/41775
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Quick Facts
Patent No.
US 12,166,079
App. No.
17/455,146
Granted
Dec 10, 2024
Kind
B2
Abstract

The present disclosure describes a 2D channel FET with low contact resistance and a method for forming such a structure. The method includes depositing a dielectric layer on a semiconductor substrate, depositing a metal layer on the dielectric layer, and depositing a hard mask layer on the metal layer. The method further includes forming a gate opening by removing a portion of the hard mask layer and a portion of the metal layer. The method further includes depositing a spacer material layer on sidewalls of the gate opening and forming a channel, the channel including a TMC layer, at a bottom of the gate opening. The method further includes forming a gate structure on the channel and in the gate opening and removing the hard mask layer.

Claims (54)

1. A method, comprising:

depositing a dielectric layer on a semiconductor substrate;

depositing a metal layer on the dielectric layer;

depositing a hard mask layer on the metal layer;

forming a gate opening by removing a portion of the hard mask layer and a first portion of the metal layer;

depositing a spacer material layer on sidewalls of the gate opening;

converting a second portion of the metal layer exposed at a bottom of the gate opening into a channel comprising a transition metal chalcogenide (TMC) layer;

forming a gate structure on the channel and in the gate opening; and

removing the hard mask layer.

2. The method of claim 1 , further comprising:

removing an other portion of the metal layer at the bottom of the gate opening prior to forming the channel.

3. The method of claim 1 , wherein converting the second portion of the metal layer comprises:

exposing the second portion of the metal layer below the gate opening to a chalcogen material-based gas or plasma at a temperature between about 300° C. and about 800° C.

4. The method of claim 1 , wherein converting the second portion of the metal layer comprises:

treating the bottom of the gate opening with a chalcogen material-based gas.

5. The method of claim 1 , wherein converting the second portion of the metal layer comprises:

forming a layer of sulfide, selenide, or telluride in the second portion of the metal layer at the bottom of the gate opening.

6. The method of claim 1 , wherein converting the second portion of the metal layer comprises converting the second portion of the metal layer into a layer of tungsten sulfide (WS 2 ), tungsten selenide (WSe 2 ), molybdenum sulfide (MoS 2 ), molybdenum selenide (MoSe 2 ), or combinations thereof.

7. The method of claim 1 , wherein the channel comprises a high mobility region at a center of the channel and a concentration profile of chalcogen atoms that decreases linearly or exponentially at ends of the channel.

8. The method of claim 1 , wherein converting the second portion of the metal layer comprises converting the second portion of the metal layer into the TMC layer with a concentration profile of chalcogen atoms, the concentration profile comprising a radiating, semicircular, diamond, or elliptical pattern.

9. The method of claim 1 , wherein converting the second portion of the metal layer comprises converting the second portion of the metal layer into the TMC layer with a rectangular, diamond, elliptical, staple-shaped, semicircular, trapezoidal, or U-shaped pattern.

10. The method of claim 1 , wherein forming the gate structure comprises:

forming a gate dielectric layer in the gate opening;

forming a work function metal (WFM) layer on the gate dielectric layer; and

forming a filler metal layer on the WFM layer.

11. A method, comprising:

depositing a first metal layer on a dielectric layer disposed on a substrate;

depositing a second metal layer on the first metal layer;

forming a gate opening by removing a portion of the first metal layer and a portion of the second metal layer;

depositing a spacer on sidewalls of the gate opening;

converting a first portion of the first metal layer exposed at a bottom of the gate opening and a second portion of the first metal layer below the spacer into a channel comprising a transition metal chalcogenide (TMC) layer; and

forming a gate structure on the channel and in the gate opening, wherein forming the gate structure comprises:

depositing a gate dielectric layer;

depositing a work function metal (WFM) layer; and

depositing a filler metal layer.

12. The method of claim 11 , further comprising:

removing an other portion of the first metal layer at the bottom of the gate opening prior to forming the channel.

13. The method of claim 11 , wherein the converting comprises:

exposing the first portion of the first metal layer below the gate opening to a chalcogen material-based gas or plasma at a temperature between about 300° C. and about 800° C.

14. The method of claim 11 , wherein the converting comprises:

treating the bottom of the gate opening with a chalcogen material-based gas at a temperature between about 500° C. and about 1100° C. and without plasma.

15. The method of claim 11 , wherein the converting comprises:

forming a layer of sulfide, selenide, or telluride in the first metal layer.

16. The method of claim 11 , wherein the converting comprises forming a layer of tungsten sulfide (WS 2 ), tungsten selenide (WSe 2 ), molybdenum sulfide (MoS 2 ), molybdenum selenide (MoSe 2 ), or combinations thereof in the first metal layer.

17. A method, comprising:

forming a dielectric layer on a substrate;

forming source/drain (S/D) regions comprising a metallic material on the dielectric layer;

forming a gate opening between the S/D regions;

forming spacers directly on sidewalls of the S/D regions exposed in the gate opening;

forming a channel comprising a transition metal chalcogenide (TMC) layer that connects the S/D regions and is in contact with the dielectric layer; and

forming a gate structure on the channel.

18. The method of claim 17 , wherein forming the channel comprises forming the channel with a mobility region at a center of the channel and a concentration profile of chalcogen atoms that decreases linearly or exponentially at ends of the channel.

19. The method of claim 17 , wherein forming the channel comprises forming a layer of sulfide, selenide, or telluride in the gate opening.

20. The method of claim 17 , wherein forming the channel comprises forming the channel with a rectangular, diamond, elliptical, staple-shaped, semicircular, trapezoidal, or U-shaped cross-sectional profile.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2022
From: KHADERBAD, MRUNAL ABHIJITH; DHANYAKUMAR, SATHAIYA MAHAVEER; WOON, WEI-YEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 060089/0883 →
Continuity (2)
Provisional Application 63159825 · Mar 11, 2021
Related Publication 20220293736A1 · Sep 15, 2022
Cited By (1)
US 12,520,562