Systems and methods for clock synchronization

1. A system for clock synchronization, comprising:

a reset signal generator connected with a plurality of detectors, wherein the reset signal generator is configured to:

generate a set of preliminary reset signals, each of which has a different phase, to be detected; and

transmit the set of preliminary reset signals to the plurality of detectors;

wherein each of the plurality of detectors is configured to:

generate first feedback data for each of the set of preliminary reset signals; and

transmit the first feedback data to the reset signal generator;

wherein the reset signal generator is further configured to:

for each of the plurality of detectors, generate a reset signal based on the first feedback data; and

transmit the reset signal to each of the plurality of detectors;

wherein each of the plurality detectors is further configured to:

execute a clock synchronization in itself based on the reset signal.

2. The system of claim 1 , wherein to generate the first feedback data for each of the set of preliminary reset signals, each of the plurality detectors is further configured to:

for each of the set of preliminary reset signals, correspondingly generate a sequence of sampling values based on a sequence of clock cycle iteration with different phases; and

take the sequence of sampling values as the first feedback data.

3. The system of claim 2 , wherein to generate the reset signal based on the first feedback data, the reset signal generator is further configured to:

determine an optimum phase of the reset signal, wherein a sampling value of a preliminary reset signal, of the plurality of the preliminary reset signal, with the optimum phase is positive, the sampling value is predicted based on the clock cycle iteration with a zero phase; and

generate the reset signal with the optimum phase.

4. The system of claim 2 , wherein to generate the reset signal based on the first feedback data, the reset signal generator is further configured to:

determine an optimum preliminary reset signal, of which a first value of the sequence of sampling values is positive; and

generate the reset signal with the phase of the optimum preliminary reset signal.

5. The system of claim 1 , wherein:

each of the plurality of detectors is further configured to:

generate second feedback data based on the reset signal; and

transmit the second feedback data to the reset signal generator;

the reset signal generator is further configured to:

determine whether the second feedback data corresponds to a predetermined value; and

in response to determining that the second feedback data corresponds to the predetermined value, transmit a determination instruction indicating that the reset signal has been correctly transmitted.

6. The system of claim 1 , wherein to generate the first feedback data for each of the set of preliminary reset signals, each of the plurality detectors is further configured to:

perform detection based on a frequency higher than a standard clock frequency;

obtain a time difference between the preliminary reset signal and the standard clock cycle; and

designate the time difference as the first feedback data.

7. The system of claim 2 , wherein for generate a sequence of sampling values based on a sequence of clock cycle iteration with different phases, each of the plurality detectors is further configured to:

generate a plurality of clock signals with different phases; and

sample a preliminary reset signal based on the plurality of clock signals to generate the sequence of sampling values of the preliminary reset signal.

8. The system of claim 3 , wherein to determine an optimum phase of the reset signal, the reset signal generator is further configured to:

determine phases of the plurality of preliminary reset signals; and

determine the optimum phase of the reset signal based on the phases of the plurality of preliminary reset signals.

9. The system of claim 8 , wherein to determine phases of the plurality of preliminary reset signals, the reset signal generator is further configured to:

determine the phase of one of the plurality of preliminary reset signals based on a relationship between a pulse signal of the preliminary reset signal and a clock cycle.

10. The system of claim 2 , wherein to generate the reset signal based on the first feedback data, the reset signal generator is further configured to:

select a preliminary reset signal corresponding to a minimum time difference from the set of preliminary reset signals as the reset signal.

11. A method for clock synchronization, comprising:

generating, by a reset signal generator connected with a plurality of detectors, a set of preliminary reset signals, each of which has a different phase, to be detected;

transmitting the set of preliminary reset signals by the reset signal generator to the plurality of detectors;

for each of the set of preliminary reset signals, generating first feedback data by each of the plurality of detectors;

transmitting the first feedback data by each of the plurality of detectors to the reset signal generator;

for each of the plurality of detectors, generating a reset signal by the reset signal generator based on the first feedback data;

transmitting the reset signal by the reset signal generator to each of the plurality of detectors; and

executing a clock synchronization in each of the plurality detectors based on the reset signal.

12. The method of claim 11 , wherein for each of the set of preliminary reset signals, the generating first feedback data by each of the plurality of detectors includes:

for each of the set of preliminary reset signals, correspondingly generating a sequence of sampling values based on a sequence of clock cycle iteration with different phases; and

taking the sequence of sampling values as the first feedback data.

13. The method of claim 12 , wherein for each of the plurality of detectors, the generating a reset signal by the reset signal generator based on the first feedback data includes:

determining an optimum phase of the reset signal, wherein a sampling value of a preliminary reset signal, of the plurality of the preliminary reset signal, with the optimum phase is positive, the sampling value is predicted based on the clock cycle iteration with a zero phase; and

generating the reset signal with the optimum phase.

14. The method of claim 12 , wherein for each of the plurality of detectors, the generating a reset signal by the reset signal generator based on the first feedback data includes:

determining an optimum preliminary reset signal, of which a first value of the sequence of sampling values is positive; and

generating the reset signal with the phase of the optimum preliminary reset signal.

15. The method of claim 11 , wherein:

generating second feedback data by each of the plurality of detectors based on the reset signal;

transmitting the second feedback data by each of the plurality of detectors to the reset signal generator;

determining, by the reset signal generator, whether the second feedback data corresponds to a predetermined value; and

in response to determining that the second feedback data corresponds to the predetermined value, transmitting, by the reset signal generator, a determination instruction indicating that the reset signal has been correctly transmitted.

16. The method of claim 12 , wherein for each of the plurality of detectors, the generating a reset signal by the reset signal generator based on the first feedback data further includes:

generating a plurality of clock signals with different phases; and

sampling a preliminary reset signal based on the plurality of clock signals to generate the sequence of sampling values of the preliminary reset signal.

17. The method of claim 12 , wherein for each of the plurality of detectors, the generating a reset signal by the reset signal generator based on the first feedback data includes:

selecting a preliminary reset signal corresponding to a minimum time difference from the set of preliminary reset signals as the reset signal.

18. The method of claim 12 , wherein for each of the plurality of detectors, the generating a reset signal by the reset signal generator based on the first feedback data further includes:

performing detection based on a frequency higher than a standard clock frequency;

obtainning a time difference between the preliminary reset signal and the standard clock cycle; and

designating the time difference as the first feedback data.

19. The method of claim 12 , wherein for each of the plurality of detectors, the generating a reset signal by the reset signal generator based on the first feedback data further includes:

determining phases of the plurality of preliminary reset signals; and

determining the optimum phase of the reset signal based on the phases of the plurality of preliminary reset signals.