Electronic chips with surface mount component
Electronic chip comprising a first integrated circuit, a second integrated circuit, a first link connecting the first integrated circuit and the second integrated circuit, a second link connecting the first integrated circuit and the second integrated circuit, a surface-mount component, the component being configured and placed to limit an electromagnetic disturbance by the first link of the second link.
1 . An electronic chip comprising:
a first integrated circuit;
a second integrated circuit;
a first link configured to transmit a first signal and connecting the first integrated circuit and the second integrated circuit;
a second link configured to transmit a second signal and connecting the first integrated circuit and the second integrated circuit; and
a surface-mount component disposed between but not directly connected to the first and second links,
wherein the first link and the second link are partially disposed on opposite sides of the surface-mount component,
wherein the surface-mount component, the first integrated circuit, and the second integrated circuit are directly mounted on a first face of a flat support, and
wherein each of the first link and the second link is directly connected to the first and second integrated circuits and contained within a volume between the first face of the flat support and a plane extending from a top face of the surface-mount component that is farthest from and parallel to the flat support.
2 . The electronic chip according to claim 1 , wherein the first link comprises at least one first electric wire, and the second link comprises at least one second electric wire.
3 . The electronic chip according to claim 1 , wherein the surface-mount component is thicker than:
the first integrated circuit, and
the second integrated circuit.
4 . The electronic chip according to claim 1 , the surface-mount component comprising:
a first metal surface layer facing the first link,
a second metal surface layer facing the second link, and
an insulating layer disposed between the first metal surface layer and the second metal surface layer.
5 . The electronic chip according to claim 1 , wherein the surface-mount component is configured to limit an electromagnetic disturbance of the second link by the first link.
6 . The electronic chip according to claim 5 , wherein the surface-mount component comprises a first surface-mount component, and a second surface-mount component disposed on the first surface-mount component, and wherein the first surface-mount component and the second surface-mount component are configured to cooperate in order to limit the electromagnetic disturbance.
7 . The electronic chip according to claim 1 , the surface-mount component having an uppermost surface above the first link and the second link.
8 . An electronic chip comprising:
a first integrated circuit;
a second integrated circuit;
a first link configured to transmit a first signal and connecting the first integrated circuit and the second integrated circuit;
a second link configured to transmit a second signal and connecting the first integrated circuit and the second integrated circuit; and
a surface-mount component,
wherein the first integrated circuit, the second integrated circuit, and the surface-mount component are directly fastened onto a first face of a flat support,
wherein the surface-mount component is fastened within a four-sided zone of the flat support defined by the first link, the second link, a first edge of the first integrated circuit, and a second edge of the second integrated circuit, and
wherein each of the first link and the second link is directly connected to the first and second integrated circuits and contained within a volume between the first face of the flat support and a plane extending from a top face of the surface-mount component that is farthest from and parallel to the flat support.
9 . The electronic chip according to claim 8 , wherein a first distance between the top face of the surface-mount component and the first face of the flat support is greater than:
a second distance between a first top of the first integrated circuit and the first face of the flat support, and
a third distance between a second top of the second integrated circuit and the first face of the flat support.
10 . The electronic chip according to claim 8 , wherein the surface-mount component is configured to limit an electromagnetic disturbance of the second link by the first link.
11 . The electronic chip according to claim 8 , the surface-mount component comprising:
a first metal surface layer facing the first link,
a second metal surface layer facing the second link, and
an insulating layer disposed between the first metal surface layer and the second metal surface layer.
12 . An electronic chip comprising:
a substrate;
a first integrated circuit directly attached to a first side of the substrate;
a second integrated circuit directly attached to the first side of the substrate;
a first electrical signal connection located above the first side of the substrate and directly interconnecting the first integrated circuit with the second integrated circuit;
a second electrical signal connection located above the first side of the substrate and directly interconnecting the first integrated circuit with the second integrated circuit;
a first surface-mount component directly attached to the first side of the substrate,
wherein the first surface-mount component is disposed between but not directly connected to the first electrical signal connection and the second electrical signal connection,
wherein the first electrical signal connection and the second electrical signal connection are partially disposed on opposite sides of the first surface-mount component; and
a second surface-mount component attached to the first surface-mount component but not directly connected to the first electrical signal connection and the second electrical signal connection,
wherein the first surface-mount component is disposed between the first side of the substrate and the second surface-mount component, and
wherein the second surface-mount component has a second uppermost surface above the first electrical signal connection and the second electrical signal connection.
13 . The electronic chip according to claim 12 , the first surface-mount component having a first uppermost surface below a third uppermost surface of the first integrated circuit and a fourth uppermost surface of the second integrated circuit.
14 . The electronic chip according to claim 13 , wherein the second uppermost surface of the second surface-mount component is above the third uppermost surface of the first integrated circuit and the fourth uppermost surface of the second integrated circuit.
15 . The electronic chip according to claim 12 , the first surface-mount component comprising:
a first metal surface layer facing the first electrical signal connection,
a second metal surface layer facing the second electrical signal connection, and
a first insulating layer isolating the first metal surface layer from the second metal surface layer.
16 . The electronic chip according to claim 15 , the second surface-mount component comprising:
a third metal surface layer facing the first electrical signal connection,
a fourth metal surface layer facing the second electrical signal connection, and
a second insulating layer isolating the third metal surface layer from the fourth metal surface layer.
17 . The electronic chip according to claim 16 , wherein the first metal surface layer is aligned with the third metal surface layer, the second metal surface layer is aligned with the fourth metal surface layer, and the first insulating layer is aligned with the second insulating layer.
18 . The electronic chip according to claim 16 , wherein the first metal surface layer is electrically coupled with and coplanar to the third metal surface layer, the second metal surface layer is electrically coupled with and coplanar to the fourth metal surface layer.
19 . The electronic chip according to claim 16 , wherein the first surface-mount component and the second surface-mount component together are configured to limit electromagnetic disturbance of the second electrical signal connection by the first electrical signal connection.
20 . The electronic chip according to claim 16 , the first surface-mount component and the second surface-mount component substantially filling a distance between the first integrated circuit and the second integrated circuit.