Phase-locked loop slip detector
A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.
1. A circuit, comprising:
a phase-locked loop (PLL) circuit; and
a lock-slip detect circuit coupled to the PLL, the lock-slip detect circuit including:
a low pass filter (LPF) having an LPF input and an LPF output;
a flip-flop having a flip-flop clock input and a flip-flop output, the flip-flop clock input coupled to the LPF output; and
a lock-slip control circuit coupled to the flip-flop output, wherein the lock-slip control circuit is configured to determine phase-lock, quasi phase-slip, and phase-slip of the PLL circuit.
2. The circuit of claim 1 , wherein:
the flip-flop has a flip-flop input, and wherein the PLL includes an inverter coupled between the flip-flop output and the flip-flop input.
3. The circuit of claim 1 , wherein:
the lock-slip control circuit receives a reference clock.
4. The circuit of claim 3 , wherein:
the lock-slip control circuit includes a counter circuit configured to count a number of edges on the flip-flop output in a predetermined number of cycles of the reference clock.
5. The circuit of claim 4 , wherein:
the lock-slip control circuit is configured to assert a lock signal indicating that the PLL is in phase-lock responsive to the number of edges being zero.
6. The circuit of claim 4 , wherein:
the lock-slip control circuit is configured to de-assert a lock signal indicating that the PLL is not in phase-lock responsive to the number of edges being greater than or equal to a first threshold number.
7. The circuit of claim 6 , wherein:
the lock-slip control circuit is configured to assert a quasi slip signal responsive to the number of edges being greater than a second threshold number and less than the first threshold number.
8. The circuit of claim 1 , wherein:
the flip-flop is coupled to a loop filter and a charge pump of the PLL circuit.
9. The circuit of claim 1 , wherein:
the LPF input is coupled to an output of a logic gate;
a first input of the logic gate is coupled to a first output of a phase-frequency detector (PFD); and
a second input of the logic gate is coupled to a second output of the PFD.
10. The circuit of claim 9 , wherein:
the logic gate is an OR gate.
11. The circuit of claim 9 , wherein:
the LPF includes a buffer having a resistance and a capacitance that determine a frequency response; and
the frequency response is configured to filter out signals from the logic gate having a pulse width below a pulse width threshold.
12. The circuit of claim 11 , wherein:
the capacitance includes a plurality of capacitors.
13. The circuit of claim 11 , wherein:
the capacitance includes a first capacitor, a second capacitor coupled to a first switch, and a third capacitor coupled to second switch.
14. The circuit of claim 13 , wherein:
the first switch and the second switch are configured to adjust the frequency response of the LPF.
15. The circuit of claim 13 , wherein:
the first switch and the second switch are controlled by a value stored in a configuration register.
16. The circuit of claim 1 , wherein:
the LPF is configured to filter signals having a pulse width less than or equal to 500 picoseconds.
17. A system, comprising:
a low pass filter (LPF) having an LPF input and an LPF output;
a flip-flop having a flip-flop clock input and a flip-flop output, the flip-flop clock input coupled to the LPF output; and
a lock-slip control circuit coupled to the flip-flop output, wherein the lock-slip control circuit is configured to output an indicator indicating one of a phase-lock and a quasi phase-slip.
18. The system of claim 17 , further comprising:
an inverter having an inverter input coupled to the flip-flop output and an inverter output coupled to a flip-flop input of the flip-flop.
19. The system of claim 17 , wherein:
the lock-slip control circuit includes a counter circuit configured to count a number of edges on the flip-flop output in a predetermined number of cycles of a reference clock;
the lock-slip control circuit is configured to assert the indicator indicating that the PLL is in phase-lock responsive to the number of edges being zero; and
the lock-slip control circuit is configured to assert the indicator indicating quasi slip responsive to the number of edges being between a first threshold and a second threshold.
20. A method for detecting slip in a phase-locked loop (PLL), comprising:
receiving, by a low pass filter (LPF), a signal from a phase-frequency detector (PFD);
filtering, by the LPF, the signal from the PFD to remove pulse widths below a first threshold to produce a filtered signal;
receiving, by a flip-flop, the filtered signal;
generating, by the flip-flop, a flip-flop output signal based on the filtered signal;
counting, by a lock-slip control circuit, a number of edges of the flip-flop output signal over a period of time;
in response to the number of edges of the flip-flop output signal being zero in the period of time, outputting, by the lock-slip control circuit, a phase-lock signal;
in response to the number of edges of the flip-flop output signal being between a second threshold and a third threshold, outputting, by the lock-slip control circuit, a quasi phase-slip signal; and
in response to the number of edges of the flip-flop output signal being at or greater than the third threshold, outputting, by the lock-slip control circuit, a phase-slip signal.