Display device

1. A display device, comprising:

a display panel divided into a display area, a non-display area, a bending area, and a pad area and bent in one direction in the bending area, the bending area being located between the non-display area and the pad area;

a plurality of pixels disposed in the display area; and

at least one electrostatic discharge circuit disposed in the pad area and connected to a discharge line extending from the pad area to the non-display area.

2. The display device of claim 1 , further comprising:

at least one gate driver disposed in the non-display area and configured to supply a gate voltage to the plurality of pixels,

wherein the at least one electrostatic discharge circuit is connected to the at least one gate driver through the discharge line.

3. The display device of claim 1 , further comprising:

flexible films connected to a plurality of pads disposed in the pad area.

4. The display device of claim 1 , wherein the discharge line overlaps the bending area.

5. The display device of claim 1 ,

wherein each of the at least one electrostatic discharge circuit is divided into a first area and a second area surrounding the first area and includes,

a plurality of transistors disposed in the first area;

connection electrodes disposed in the second area and configured to connect the plurality of transistors and the discharge line;

a planarization layer configured to cover the plurality of transistors and comprised of an organic material; and

a passivation layer disposed on the planarization layer and comprised of an inorganic material.

6. The display device of claim 5 ,

wherein a first trench is formed in the planarization layer in the second area.

7. The display device of claim 6 ,

wherein the first trench overlaps the connection electrode and surrounds the first area.

8. The display device of claim 6 ,

wherein the planarization layer is separated into an inner planarization layer and an outer planarization layer by the first trench, and

wherein the plurality of transistors are disposed below the internal planarization layer.

9. The display device of claim 6 ,

wherein a second trench is formed in the passivation layer in the second area.

10. The display device of claim 9 ,

wherein the second trench overlaps the connection electrode and surrounds the first area.

11. The display device of claim 9 ,

wherein the passivation layer is separated into an inner passivation layer and an outer passivation layer by the second trench, and

wherein the plurality of transistors are disposed below the internal passivation layer.

12. The display device of claim 9 ,

wherein the second trench is formed within the first trench.

13. The display device of claim 12 , wherein a side surface of the planarization layer formed in the first trench is covered by the passivation layer.

14. The display device of claim 12 , wherein a width of the second trench is smaller than a width of the first trench.

15. The display device of claim 5 ,

wherein the plurality of transistors include,

a first transistor connected to a low potential voltage line; and

a second transistor connected to a high potential voltage line.

16. The display device of claim 15 , wherein a source electrode and a gate electrode of the first transistor are connected to the discharge line and a drain electrode of the first transistor is connected to the low potential voltage line, and

wherein a drain electrode and a gate electrode of the second transistor are connected to the discharge line and a source electrode of the second transistor is connected to the high potential voltage line.

17. The display device of claim 15 , wherein the low potential voltage line and the high potential voltage line are disposed on the same layer as a gate electrode of each of the plurality of transistors.

18. The display device of claim 5 ,

wherein the discharge line is disposed on the same layer as a source electrode and a drain electrode of each of the plurality of transistors.

19. The display device of claim 5 ,

wherein the connection electrodes are disposed on the same layer as a gate electrode of each of the plurality of transistors.