Stiffener package and method of fabricating stiffener package
A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.
1. An electronic package comprising:
a semiconductor die comprising:
a first die side;
a second die side opposite the first die side and comprising a die interconnect (DI), where the die interconnect (DI) comprises a first DI side and a second DI side; and
a lateral die side that extends between the first die side and the second die side;
a stiffener positioned laterally outward from the lateral die side, the stiffener comprising a first stiffener side that is parallel to the first die side, and a second stiffener side that is parallel to the second die side;
a vertical interconnect structure (VIS) that passes vertically through the stiffener, the vertical interconnect structure (VIS) comprising a first VIS side, and a second VIS side opposite the first VIS side, where the second VIS side is coplanar with the second DI side and the second stiffener side;
a first conductor on the first stiffener side, where the first conductor is electrically connected to the first VIS side;
a first dielectric on the first stiffener side and on the first die side, where:
the first dielectric contacts the first stiffener side; and
the first dielectric laterally surrounds at least a portion of the first conductor; and
a signal distribution structure (SDS) comprising:
an SDS conductor on the second stiffener side and on the second die side, where the SDS conductor is electrically connected to the second VIS side and is electrically connected to the die interconnect (DI); and
an SDS dielectric on the second stiffener side and on the second die side, where:
the SDS dielectric contacts the second stiffener side; and
the SDS dielectric laterally surrounds at least a portion of the SDS conductor.
2. The electronic package of claim 1 , wherein the stiffener laterally surrounds an entirety of the vertical interconnect structure (VIS).
3. The electronic package of claim 1 , wherein the stiffener comprises a lateral stiffener side that extends between the first stiffener side and the second stiffener side, where the lateral stiffener side is a laterally outermost side of the electronic package.
4. The electronic package of claim 1 , wherein:
the die interconnect (DI) comprises a bond pad; and
the second DI side comprises a surface of the bond pad.
5. The electronic package of claim 1 , wherein the first dielectric contacts the first die side.
6. The electronic package of claim 5 , wherein:
the first dielectric contacts only a portion of the first stiffener side; and
the first dielectric comprises an opening through which the first VIS side is exposed.
7. The electronic package of claim 1 , wherein the vertical interconnect structure (VIS) comprises plated copper.
8. The electronic package of claim 1 , wherein the semiconductor die comprises a sensor circuit.
9. The electronic package of claim 1 , wherein:
the first conductor comprises a first ball pad on the first stiffener side; and
the SDS conductor comprises an SDS horizontal trace on the second stiffener side and on the second die side, where the SDS horizontal trace is electrically connected to the second VIS side and is electrically connected to the die interconnect (DI).
10. An electronic package comprising:
a semiconductor die comprising:
a first die side;
a second die side opposite the first die side and comprising a die interconnect (DI), where the die interconnect (DI) comprises a first DI side and a second DI side; and
a lateral die side that extends between the first die side and the second die side;
a stiffener positioned laterally outward from the lateral die side, the stiffener comprising a first stiffener side that is parallel to the first die side, and a second stiffener side that is parallel to the second die side;
a vertical interconnect structure (VIS) that passes vertically through the stiffener, the vertical interconnect structure (VIS) comprising a first VIS side, and a second VIS side opposite the first VIS side;
a first conductor on the first stiffener side, where the first conductor is electrically connected to the first VIS side;
a first dielectric on the first stiffener side and on the first die side, where:
the first dielectric contacts the first stiffener side and the first die side; and
the first dielectric laterally surrounds at least a portion of the first conductor; and
a signal distribution structure (SDS) comprising:
an SDS conductor on the second stiffener side and on the second die side, where the SDS conductor is electrically connected to the second VIS side and is electrically connected to the die interconnect (DI); and
an SDS dielectric on the second stiffener side and on the second die side, where:
the SDS dielectric contacts the second stiffener side; and
the SDS dielectric laterally surrounds at least a portion of the SDS conductor.
11. The electronic package of claim 10 , wherein:
the first dielectric contacts only a portion of the first stiffener side; and
the first dielectric comprises an opening through which the first VIS side is exposed.
12. The electronic package of claim 10 , wherein the stiffener comprises a lateral stiffener side that extends between the first stiffener side and the second stiffener side, where the lateral stiffener side is a laterally outermost side of the electronic package.
13. The electronic package of claim 10 , wherein the stiffener contacts the semiconductor die.
14. The electronic package of claim 10 , wherein:
the first dielectric contacts the first die side;
the first dielectric contacts only a portion of the first stiffener side; and
the first dielectric comprises an opening through which the first VIS side is exposed.
15. The electronic package of claim 10 , wherein the first stiffener side is substantially coplanar with the first VIS side and with the first DI side.
16. The electronic package of claim 10 , wherein:
the first conductor comprises a first ball pad on the first stiffener side; and
the SDS conductor comprises an SDS horizontal trace on the second stiffener side and on the second die side, where the SDS horizontal trace is electrically connected to the second VIS side and is electrically connected to the die interconnect (DI).
17. A method of manufacturing an electronic package, the method comprising:
providing a structure comprising:
a semiconductor die comprising:
a first die side;
a second die side opposite the first die side and comprising a die interconnect (DI), where the die interconnect (DI) comprises a first DI side and a second DI side; and
a lateral die side that extends between the first die side and the second die side;
a stiffener positioned laterally outward from the lateral die side, the stiffener comprising a first stiffener side that is parallel to the first die side, and a second stiffener side that is parallel to the second die side;
a vertical interconnect structure (VIS) that passes vertically through the stiffener, the vertical interconnect structure (VIS) comprising a first VIS side, and a second VIS side opposite the first VIS side;
a first conductor on the first stiffener side, where the first conductor is electrically connected to the first VIS side; and
a first dielectric on the first stiffener side and on the first die side, where:
the first dielectric contacts the first stiffener side; and
the first dielectric laterally surrounds at least a portion of the first conductor; and
providing a signal distribution structure (SDS) comprising:
an SDS conductor on the second stiffener side and on the second die side, where the SDS conductor is electrically connected to the second VIS side and is electrically connected to the die interconnect (DI); and
an SDS dielectric on the second stiffener side and on the second die side, where:
the SDS dielectric contacts the second stiffener side; and
the SDS dielectric laterally surrounds at least a portion of the SDS conductor.
18. The method of claim 17 , wherein the second VIS side is coplanar with the second DI side and the second stiffener side.
19. The method of claim 17 , wherein the first dielectric contacts the first die side.
20. The method of claim 17 , wherein the stiffener laterally surrounds an entirety of the vertical interconnect structure (VIS).