Semiconductor device
A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.
1. A semiconductor device comprising:
an active pattern including a lower pattern and a plurality of sheet patterns disposed above the lower pattern and spaced apart from the lower pattern;
a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and
a source/drain pattern filling a source/drain recess and formed on at least one side of the gate structure,
wherein the source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second semiconductor pattern disposed on the first semiconductor pattern, and a third semiconductor pattern disposed on the second semiconductor pattern,
a lowermost surface of the third semiconductor pattern is disposed below a lowermost surface of a lowermost sheet pattern of the plurality of sheet patterns,
a side surface of the third semiconductor pattern, which is a boundary between the third semiconductor pattern and the second semiconductor pattern, includes a planar portion,
the lowermost surface of the third semiconductor pattern includes a planar portion,
a lowermost surface of the second semiconductor pattern includes a planar portion,
a length of the planar portion of the lowermost surface of the second semiconductor pattern is smaller than a length of the planar portion of the lowermost surface of the third semiconductor pattern, and
a thickness of the second semiconductor pattern on the lowermost surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.
2. The semiconductor device of claim 1 , wherein the thickness of the second semiconductor pattern on the lowermost surface of the third semiconductor pattern is greater than the thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.
3. The semiconductor device of claim 1 , wherein a thickness of the first semiconductor pattern on the lowermost surface of the third semiconductor pattern is different from a thickness of the first semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.
4. The semiconductor device of claim 3 , wherein the thickness of the first semiconductor pattern on the lowermost surface of the third semiconductor pattern is greater than the thickness of the first semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.
5. The semiconductor device of claim 1 , wherein
the source/drain pattern further includes a fourth semiconductor pattern that is disposed on the third semiconductor pattern and fills the source/drain recess, and
an upper surface of the fourth semiconductor pattern includes a planar portion.
6. The semiconductor device of claim 1 , wherein
the source/drain pattern further includes a fourth semiconductor pattern that is disposed on the third semiconductor pattern and fills the source/drain recess, and
an upper surface of the fourth semiconductor pattern includes an upwardly convex portion.
7. The semiconductor device of claim 1 , wherein
the source/drain pattern further includes a fourth semiconductor pattern that is disposed on the third semiconductor pattern and fills the source/drain recess, and
an upper surface of the fourth semiconductor pattern is disposed below an upper surface of an uppermost sheet pattern of the plurality of sheet patterns, and includes a downwardly convex portion.
8. The semiconductor device of claim 7 , wherein the upper surface of the fourth semiconductor pattern is disposed above an upper surface of a sheet pattern of the plurality of sheet patterns adjacent to the uppermost sheet pattern of the plurality of sheet patterns.
9. The semiconductor device of claim 1 , wherein a thickness of the first semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern decreases and then increases at a portion of the first semiconductor pattern in contact with the gate structure as it moves away from the lower pattern.
10. A semiconductor device comprising:
a substrate;
an active pattern extending in a first direction on the substrate;
a gate structure disposed on the active pattern and extending in a second direction different from the first direction; and
a source/drain pattern filling a source/drain recess and formed on at least one side of the gate structure,
wherein the source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the active pattern, a second semiconductor pattern disposed on the first semiconductor pattern, a third semiconductor pattern disposed on the second semiconductor pattern, and a fourth semiconductor pattern that is disposed on the third semiconductor pattern and fills the source/drain recess,
a side surface of the third semiconductor pattern, which is a boundary between the third semiconductor pattern and the second semiconductor pattern, includes an upper portion and a lower portion,
a distance between the lower portion of the side surface of the third semiconductor pattern and the active pattern in the first direction is substantially constant,
a lowermost surface of the third semiconductor pattern includes a planar portion,
a lowermost surface of the second semiconductor pattern includes a planar portion, and
a length of the planar portion of the lowermost surface of the second semiconductor pattern is smaller than a length of the planar portion of the lowermost surface of the third semiconductor pattern.
11. The semiconductor device of claim 10 , wherein the active pattern is a fin-type pattern.
12. The semiconductor device of claim 10 , wherein the active pattern includes a lower pattern disposed on the substrate and a plurality of sheet patterns disposed above the lower pattern and spaced apart from the lower pattern in a third direction different from the first direction and the second direction.
13. The semiconductor device of claim 10 , wherein
each of the first semiconductor pattern, the second semiconductor pattern, the third semiconductor pattern, and the fourth semiconductor pattern includes silicon-germanium,
a germanium fraction of the fourth semiconductor pattern is greater than a germanium fraction of the third semiconductor pattern,
the germanium fraction of the third semiconductor pattern is greater than a germanium fraction of the second semiconductor pattern, and
the germanium fraction of the second semiconductor pattern is greater than a germanium fraction of the first semiconductor pattern.
14. The semiconductor device of claim 10 , wherein
the planar portion of the lowermost surface of the second semiconductor pattern overlaps the planar portion of the third semiconductor pattern in a third direction different from the first direction and the second direction.
15. A semiconductor device comprising:
an active pattern including a lower pattern and a plurality of sheet patterns disposed above the lower pattern and spaced apart from the lower pattern;
a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and
a source/drain pattern filling a source/drain recess and formed on at least one side of the gate structure,
wherein the source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second semiconductor pattern disposed on the first semiconductor pattern and extending along the first semiconductor pattern, a third semiconductor pattern disposed on the second semiconductor pattern and extending along the second semiconductor pattern, and a fourth semiconductor pattern that is disposed on the third semiconductor pattern and fills the source/drain recess,
a lowermost surface of the third semiconductor pattern is disposed below a lowermost surface of a lowermost sheet pattern of the plurality of sheet patterns,
a side surface of the third semiconductor pattern, which is a boundary between the third semiconductor pattern and the second semiconductor pattern, includes a first planar portion, and
an upper surface of the fourth semiconductor pattern includes a second planar portion or an upwardly convex portion,
the lowermost surface of the third semiconductor pattern includes a third planar portion,
a lowermost surface of the second semiconductor pattern includes a fourth planar portion, and
a length of the fourth planar portion is smaller than a length of the third planar portion.
16. The semiconductor device of claim 15 , wherein
the gate structure includes a gate electrode and a gate insulating layer disposed between the gate electrode and the source/drain pattern, and
the first semiconductor pattern is in contact with the gate insulating layer and the plurality of sheet patterns.
17. The semiconductor device of claim 15 , wherein
the side surface of the third semiconductor pattern, which is the boundary between the third semiconductor pattern and the second semiconductor pattern, includes an upper portion and a lower portion that includes the first planar portion, and
the first planar portion overlaps the lowermost sheet pattern of the plurality of sheet patterns and a sheet pattern of the plurality of sheet patterns adjacent to the lowermost sheet pattern in a direction in which the active pattern extends.
18. The semiconductor device of claim 17 , wherein the first planar portion overlaps at least a portion of an uppermost sheet pattern of the plurality of sheet patterns in the direction in which the active pattern extends.